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Re: negative latencies

On 23-May-14 05:20 PM, Vladimir Makarov wrote:
On 2014-05-23, 3:49 AM, shmeel gutl wrote:
On 21-May-14 06:30 PM, Vladimir Makarov wrote:
I am just curious what happens when you put

insn2, insn1.

and insn2 uses a result of insn1 in 6 cycles and insn1 producing the
result in 3 cycles, but there are not ready functional units (e.g.
arithmentic units) necessary for insn1 for 4 or more cycles. It is
quite not trivial to guarantee that everything will be okay in general
case if you put insn2 before insn1.

This is not a problem for this architecture. The units are fully
pipelined and the only conflicts are in the first stage, during
instruction issue. That is, the vliw must be legal. The gcc dfa handles
this case fine.

Another problem is that besides insn-scheduler there are a lot of optimizations which can insert some insns between the two insns after scheduling. In this case the result might be not ready for insn2.

So you at least should exclude 1st insn scheduling (before RA) and make 2nd insn scheduling as the very last pass.

In general, a traditional approach is to do such things on assembler level (e.g. as for older MIPS processor without hardware interlocks).

There is also IRA. I would need to tweak the definition of live range.

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