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Re: negative latencies
- From: shmeel gutl <shmeelgutl at shmuelhome dot mine dot nu>
- To: Bernd Schmidt <bernds at codesourcery dot com>, Vladimir Makarov <vmakarov at redhat dot com>, "gcc at gcc dot gnu dot org" <gcc at gcc dot gnu dot org>
- Date: Mon, 26 May 2014 08:49:54 +0300
- Subject: Re: negative latencies
- Authentication-results: sourceware.org; auth=none
- References: <5379A125 dot 5090405 at shmuelhome dot mine dot nu> <537B7121 dot 6080408 at redhat dot com> <537BC690 dot 2030807 at shmuelhome dot mine dot nu> <537CC6A8 dot 6090607 at redhat dot com> <537E23F2 dot 9020302 at codesourcery dot com> <537F01B0 dot 5040200 at shmuelhome dot mine dot nu> <537F29FC dot 8010707 at codesourcery dot com>
On 23-May-14 01:59 PM, Bernd Schmidt wrote:
Okay, I think that I have the idea. But I would still need to backtrack
if the enabling instruction is not issued on time. I would also need to
delay the dependent instruction if I can see in advance that the
producer cannot be issued on time. And, as Vladimir pointed out, I need
to watch out for various passes inserting unwanted instructions. Sounds
like a big project.
On 05/23/2014 10:07 AM, shmeel gutl wrote:
Exposed pipeline is not my problem. Negative latency is my problem. I
don't see negative latency for c6x, not in unit reservations and not in
adjust cost. Did I miss something?
You just need to model it differently. Rather than saying instruction
A has a negative latency relative to instruction B, you need to
describe that instruction B reads its inputs later than when it is
actually issued. The mechanism used in the C6X backend is the
scheduler's record_delay_slot_pair function.
The scheduler would see
B is issued (*)
A is issued, executes and writes its outputs
<some more cycles>
B reads its inputs (*)
The two insns marked as (*) would be such a delay pair. The first one
would generate code, the second one exists only for the purposes of
building the right scheduling dependencies.