This is the mail archive of the mailing list for the GCC project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: negative latencies

On 23-May-14 01:59 PM, Bernd Schmidt wrote:
On 05/23/2014 10:07 AM, shmeel gutl wrote:

Exposed pipeline is not my problem. Negative latency is my problem. I
don't see negative latency for c6x, not in unit reservations and not in
adjust cost. Did I miss something?

You just need to model it differently. Rather than saying instruction A has a negative latency relative to instruction B, you need to describe that instruction B reads its inputs later than when it is actually issued. The mechanism used in the C6X backend is the scheduler's record_delay_slot_pair function.

The scheduler would see

B is issued (*)
<some cycles>
A is issued, executes and writes its outputs
<some more cycles>
B reads its inputs (*)

The two insns marked as (*) would be such a delay pair. The first one would generate code, the second one exists only for the purposes of building the right scheduling dependencies.


Okay, I think that I have the idea. But I would still need to backtrack if the enabling instruction is not issued on time. I would also need to delay the dependent instruction if I can see in advance that the producer cannot be issued on time. And, as Vladimir pointed out, I need to watch out for various passes inserting unwanted instructions. Sounds like a big project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]