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Re: negative latencies

On 05/21/2014 05:30 PM, Vladimir Makarov wrote:
On 2014-05-20, 5:18 PM, shmeel gutl wrote:
The problem that I see is that the haifa scheduler schedules one cycle
at a time, in a forward order, by picking from a list of instructions
that can be scheduled without delays. So, in the above example, if
instruction one is scheduled during cycle 3, it can't schedule
instruction two during cycle 0, 1, or 2 because its producer dependency
(instruction one) hasn't been scheduled yet. It won't be able to
schedule it until cycle 3. So I am asking if there is an existing
mechanism to back schedule instruction two once instruction one is

I see, thanks.  There is no such mechanism in the current insn

Well, the scheduler has support for an exposed pipeline that is used by the C6X port. Insns are split into multiple pieces which are forced to be scheduled at a fixed distance in time from each other, each piece describing the effects that occur at that point in time. This could probably be made to work for this target's requirements, but it might run quite slowly.


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