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Re: negative latencies
- From: Vladimir Makarov <vmakarov at redhat dot com>
- To: shmeel gutl <shmeelgutl at shmuelhome dot mine dot nu>, "gcc at gcc dot gnu dot org" <gcc at gcc dot gnu dot org>
- Date: Wed, 21 May 2014 11:30:48 -0400
- Subject: Re: negative latencies
- Authentication-results: sourceware.org; auth=none
- References: <5379A125 dot 5090405 at shmuelhome dot mine dot nu> <537B7121 dot 6080408 at redhat dot com> <537BC690 dot 2030807 at shmuelhome dot mine dot nu>
On 2014-05-20, 5:18 PM, shmeel gutl wrote:
On 20-May-14 06:13 PM, Vladimir Makarov wrote:
On 05/19/2014 02:13 AM, shmeel gutl wrote:
Are there hooks in gcc to deal with negative latencies? In other
words, an architecture that permits an instruction to use a result
from an instruction that will be issued later.
Could you explain more on *an example* what are you trying to achieve
with the negative latency.
Scheduler is based on a critical path algorithm. Generally speaking
latency time can be negative for this algorithm. But I guess that is
not what you are asking.
The architecture has an exposed pipeline where instructions read
registers during the required cycle. So if one instruction produces its
results in the third pipeline stage and a second instruction reads the
register in the sixth pipeline stage, the second instruction can read
the results of the first instruction even if it is issued three cycles
The problem that I see is that the haifa scheduler schedules one cycle
at a time, in a forward order, by picking from a list of instructions
that can be scheduled without delays. So, in the above example, if
instruction one is scheduled during cycle 3, it can't schedule
instruction two during cycle 0, 1, or 2 because its producer dependency
(instruction one) hasn't been scheduled yet. It won't be able to
schedule it until cycle 3. So I am asking if there is an existing
mechanism to back schedule instruction two once instruction one is issued.
I see, thanks. There is no such mechanism in the current insn
scheduler. A lot of things should be done to implement this. It is
possible but it will be not easy, the insn scheduler is already quite
complicated as it supports too many things.
I am just curious what happens when you put
and insn2 uses a result of insn1 in 6 cycles and insn1 producing the
result in 3 cycles, but there are not ready functional units (e.g.
arithmentic units) necessary for insn1 for 4 or more cycles. It is
quite not trivial to guarantee that everything will be okay in general
case if you put insn2 before insn1.