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Re: negative latencies


On 19-May-14 01:02 PM, Ajit Kumar Agarwal wrote:
Is it the case of code speculation where the negative latencies are used?
No. It is an exposed pipeline where instructions read registers during the required cycle. So if one instruction produces its results in the third pipeline stage and a second instruction reads the register in the sixth pipeline stage. The second instruction can read the results of the first instruction even if it is issued three cycles earlier.

Thanks & Regards
Ajit
-----Original Message-----
From: gcc-owner@gcc.gnu.org [mailto:gcc-owner@gcc.gnu.org] On Behalf Of shmeel gutl
Sent: Monday, May 19, 2014 12:23 PM
To: Andrew Pinski
Cc: gcc@gcc.gnu.org; Vladimir Makarov
Subject: Re: negative latencies

On 19-May-14 09:39 AM, Andrew Pinski wrote:
On Sun, May 18, 2014 at 11:13 PM, shmeel gutl
<shmeelgutl@shmuelhome.mine.nu> wrote:
Are there hooks in gcc to deal with negative latencies? In other
words, an architecture that permits an instruction to use a result
from an instruction that will be issued later.
Do you mean bypasses?  If so there is a bypass feature which you can use:
https://gcc.gnu.org/onlinedocs/gccint/Processor-pipeline-description.h
tml#index-data-bypass-3773

Thanks,
Andrew Pinski
Unfortunately, bypasses in the pipeline description is not enough.
They only allow you to calculate the latency of true dependencies. They are also forced to be zero or greater. The real question is how the scheduler and register allocator can deal with negative latencies.

Thanks
Shmeel
At first glance it seems that it will will break a few things.
1) The definition of dependencies cannot come from the simple
ordering of rtl.
2) The scheduling problem starts to look like "get off the train 3
stops before me".
3) The definition of live ranges needs to use actual instruction
timing information, not just instruction sequencing.

The hooks in the scheduler seem to be enough to stop damage but not
enough to take advantage of this "feature".

Thanks

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