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SPARC LEON3 and CAS instruction


recent GCC versions support the C11 atomic operations for the SPARC LEON3 processor via the CASA instruction. GCC emits CASA instructions with an ASI of 0x80. I think this is due to the usage of "cas" if I get the stuff in right:

"(define_insn "*atomic_compare_and_swap<mode>_1"
  [(set (match_operand:I48MODE 0 "register_operand" "=r")
	(match_operand:I48MODE 1 "mem_noofs_operand" "+w"))
   (set (match_dup 1)
	  [(match_operand:I48MODE 2 "register_operand" "r")
	   (match_operand:I48MODE 3 "register_operand" "0")]
  "(TARGET_V9 || TARGET_LEON3) && (<MODE>mode != DImode || TARGET_ARCH64)"
  "cas<modesuffix>\t%1, %2, %0"
  [(set_attr "type" "multi")])"

According to the LEON3 manual we have:

"6.2.7 Compare and Swap instruction (CASA)

LEON4 implements the SPARC V9 Compare and Swap Alternative (CASA) instruction. The CASA operates as described in the SPARC V9 manual. The instruction is privileged, except when setting ASI = 0xA (user data)."

I would like to use atomic operations in user mode. Is it possible to add a machine option to GCC to use an ASI of 0x0A for the atomic operations via CASA on LEON3?

Sebastian Huber, embedded brains GmbH

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