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Re: Regarding x86 'sete' instruction and its corresponding RTL


> ----------------------------------------------------------------
> RTL: (set (reg:QI 0 ax)
>                  (eq:QI (reg:CCZ 17 flags) (const_int 0)))
> 
> Assembly: sete %al
> ----------------------------------------------------------------
> 
> Semantics of sete instruction is (as per Intel manual):
>   if zero flag = 1, (reg:QI ax)  = 1
>   else (reg:QI ax) = 0
> 
> Where as (I believe) RTL semantics seems to say that:
>  - if zero flag = 0, (reg:QI ax) = 1
>    else (reg:QI ax) = 0
> 
> This is because 'eq' operator returns STORE_FLAG_VALUE when both
> operands of 'eq' are equal. Otherwise, it returns 0. This is exactly
> opposite of what assembly semantics is.

No, that's wrong, the semantics of the comparison operators applied to the CC 
register have nothing to do with STORE_FLAG_VALUE (see manual section 13.10).

 
Eric Botcazou


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