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Re: Asm volatile causing performance regressions on ARM
- From: Richard Biener <richard dot guenther at gmail dot com>
- To: Eric Botcazou <ebotcazou at adacore dot com>
- Cc: GCC Development <gcc at gcc dot gnu dot org>, Pavel Fedin <p dot fedin at samsung dot com>
- Date: Fri, 28 Feb 2014 10:50:44 +0100
- Subject: Re: Asm volatile causing performance regressions on ARM
- Authentication-results: sourceware.org; auth=none
- References: <02f001cf3447$b7cb7380$27625a80$%garbuzov at samsung dot com> <3633543 dot TNsZsBs1fu at polaris> <CAFiYyc1H+coFv8D9xjqEbX5kQ6bZoPZEnm_SbCdpMzpyY3mRtQ at mail dot gmail dot com> <7225053 dot he9z7biE2k at polaris>
On Fri, Feb 28, 2014 at 10:23 AM, Eric Botcazou <ebotcazou@adacore.com> wrote:
>> Of course if the GIMPLE level doesn't care about the barrier then it doesn't
>> make sense to be overly conservative at the RTL CSE level. Thus I think we
>> can just remove this barrier completely.
>
> Not clear to me, what happens e.g. for register variables?
Not sure, on GIMPLE some passes explicitely avoid doing some transforms
for DECL_HARD_REGISTER variables, some don't. A volatile asm is
certainly not considered a barrier here (DECL_HARD_REGISTER vars are
not written into SSA form but they are not having their address taken
and thus the volatile asm memory clobber isn't a barrier for them).
Richard.