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post_inc mem in parallel rtx
- From: BELBACHIR Selim <selim dot belbachir at fr dot thalesgroup dot com>
- To: "gcc at gcc dot gnu dot org" <gcc at gcc dot gnu dot org>
- Date: Fri, 22 Nov 2013 17:43:47 +0100
- Subject: post_inc mem in parallel rtx
- Authentication-results: sourceware.org; auth=none
I encountered a bug in cselib.c:2360 using gnat7.1.2 (gcc4.7.3)
/* The register should have been invalidated. */
gcc_assert (REG_VALUES (dreg)->elt == 0); <<== assert(false)
I investigated the dump and found that the crash occurred during 207r.dse2 pass.
Here is what I saw in the previous dump (206r.pro_and_epilogue) :
(insn 104 47 105 7 (parallel [
(set (reg:CC_NOOV 56 $CCI)
(compare:CC_NOOV (minus:SI (reg/f:SI 22 $R6 [orig:133 D.3274 ] )
(mem/f:SI (post_inc:SI (reg:SI 2 $R2 [orig:140 ivtmp.363 ] )) [0 MEM[base: D.4517_59, offset: 0B]+0 S4 A32]))
(const_int 0 )))
(set (reg:SI 16 $R0 )
(minus:SI (reg/f:SI 22 $R6 [orig:133 D.3274 ] )
(mem/f:SI (post_inc:SI (reg:SI 2 $R2 [orig:140 ivtmp.363 ] )) [0 MEM[base: D.4517_59, offset: 0B]+0 S4 A32])))
Note the post_inc MEM on $R2 appearing twice
This rtl match my pattern (predicate and contraint ok) below :
[(set (reg:CC_NOOV CCI_REG)
(match_operand:SI 1 "general_operand" "g")
(match_operand:SI 2 " general_operand " " g"))
(set (match_operand:SI 0 "register_operand" "=r ")
But I think It may be an error to authorize post_inc MEM in this parallel rtx in operand 1 & 2.
When I put a more restrictive constraint which forbid the use of post_inc, the crash in cselib.c disappear.
Question : What does GCC understand when the md describes a pattern allowing the same post_inc MEM in 2 slot of a parallel rtx ?
Is it forbidden ? the MEM address is supposed to be incremented twice ?