Re: conflict between scheduler and register allocator

[Vladimir Makarov <vmakarov at redhat dot com>]

On 13-08-09 7:25 AM, shmeel gutl wrote:
> I am having trouble meeting the constraints of the scheduler and the 
> register allocator for my back end. The relevant features are:
>
> 1) VLIW - up to 4 instructions can be issued each cycle
> 2) If a vliw bundle has both a set and a use, the use will use the old 
> values.
> 3) A call instruction will push r30 and r31 to the stack making them 
> natural candidates for callee saved.
>
> The problem is that the scheduler might include an instruction that 
> sets r30 in the same vliw as a call. This would result in a stale 
> value being saved to the stack. (Note: the call instruction is not 
> truly dependent on r30, just that r30 can't be set in the vliw that 
> contains the call). On the other hand, if I declare that the call uses 
> r30, the register allocator will refuse to use r30 since it thinks 
> that the register is live.
> I know that I can use a hook to fix-up the first problem by breaking a 
> single vliw into two bundles, but that has a performance penalty. Is 
> there a way to tell the scheduler to avoid issuing an instruction that 
> sets a30 or a31 in the same bundle that contains a call instruction?
>
> Thank you for any pointers.
You should look at haifa-sched.c::schedule_block.   There are a lot of 
hooks called at different stages of list scheduling algorithm. Depending 
on what the algorithm stage you want to do this, you can use a specific 
hook.  I'd pay attention to targetm.sched.reorder[2].

You also can look at the hooks implemented for IA64 as it is most widely 
used VLIW architecture for now.  But implementation of some IA64 hook 
are pretty big.