Re: Why high vsr registers [vsr32 - vsr63] are not used when -mvsx is specified on powerpc?

[Carrot Wei <carrot at google dot com>]

On Wed, Jul 17, 2013 at 6:01 PM, David Edelsohn <dje.gcc@gmail.com> wrote:
> On Wed, Jul 17, 2013 at 7:27 PM, Carrot Wei <carrot@google.com> wrote:
>> Hi
>>
>> When I tried to build 444.namd with options "-O2 -m64 -mvsx
>> -mcpu=power7", I can see vsx instructions are actually used, there are
>> many xs- started instructions, but none of them use high registers
>> [vsr32 -vsr63], does anybody know the reason?
>>
>> One example is function calc_pair_energy_fullelect in file
>> ComputeNonbondedUtil.o, there are many vsr register spilling but high
>> vsr registers are never used.
>
> For scalar floating point, not vector floating point, GCC currently
> uses only the lower VSRs because the upper registers only allow
> indexed addressing modes (register + register) and not displacement
> forms.  It's one register class with different valid addressing forms
> depending on the register number, which is difficult for GCC. We did
> not want to disable displacement address form in the initial support.

In insn patterns the register class is usually not directly used, instead
different predicates and constraints are used. So can we use different
predicates and constraints in memory access instructions and floating
point arithmetic instructions?

>
> Mike Meissner currently is working on patches for the PPC backend to
> improve this through reload hooks.
Great to hear this. It will be better if the high registers can be
used at allocation time.

thanks
Carrot