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Pushing the limits on vector modes


Hello,

I am trying to model a predicate register mode that acts like a vector. We have a few predicate registers that have 8 bits in size but they are set accordingly to the mode of operation (not necessarily a comparison). Word size is 64.

Here's an example, for a scalar comparison leq p0, r0, 1: p0 will be set to 0xff if r0 <= but if I use simd operations the predicate register is not set as a single register.
For example, if I do tsteqw p0, r0, 0x0000 0000 0000 0001 (test equal on 32bits at a time), p0 will be 0b11110000. I could use tsteqb p0, r0, 0x0100 0100 0100 0100 (test equal on 8bits at a time), p0 will be 0b01010101.

It seems to me that the best way to represent this is by using a vector mode of BIs.
So in modes.def:
FRACTIONAL_INT_MODE (B2, 2, 1); // Two bits
FRACTIONAL_INT_MODE (B4, 4, 1); // Four bits
// use QI for 8 bits and BI for 1 bit

VECTOR_MODE (INT, BI, 8);
VECTOR_MODE (INT, B2, 4);
VECTOR_MODE (INT, B4, 2);
VECTOR_MODE (INT, QI, 1); // which probably doesn't make sense and QImode can simply be used instead.

Then I could model tsteqw as:
(define_insn "*tsteqw"
  [(set (match_operand:V2B4 0 "predicate_register" "=p")
        (eq:V2B4 (match_operand:V2SI 1 "register_operand")
                 (match_operand:V2SI 2 "general_operand")))]
  ...)

Is this something reasonable or will GCC simply choke since I am pushing the limits of vector modes?        

Paulo Matos



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