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RE: Modeling predicate registers with more than one bit
- From: "Paulo Matos" <pmatos at broadcom dot com>
- To: "Hans-Peter Nilsson" <hp at bitrange dot com>
- Cc: "gcc at gcc dot gnu dot org" <gcc at gcc dot gnu dot org>
- Date: Thu, 28 Mar 2013 13:26:29 +0000
- Subject: RE: Modeling predicate registers with more than one bit
- References: <19EB96622A777C4AB91610E763265F461AE5A2 at SJEXCHMB14 dot corp dot ad dot broadcom dot com> <alpine dot BSF dot 2 dot 02 dot 1303042030210 dot 15765 at arjuna dot pair dot com> <19EB96622A777C4AB91610E763265F461B265E at SJEXCHMB14 dot corp dot ad dot broadcom dot com> <alpine dot BSF dot 2 dot 02 dot 1303261334480 dot 16035 at arjuna dot pair dot com>
> -----Original Message-----
> From: Hans-Peter Nilsson [mailto:hp@bitrange.com]
> Sent: 26 March 2013 17:43
> To: Paulo Matos
> Cc: gcc@gcc.gnu.org
> Subject: RE: Modeling predicate registers with more than one bit
> >
> > What do you mean by source modes?
>
> The SI and HI in subsi3 and subhi3. IIRC you said your ISA set
> CC-bits differently depending on the size of the operand.
>
That's true. And I am starting to think that CCMODE is exactly what I need.
Even though my predicate register is QImode (8 bits), only certain bits are set depending on source modes. I can I can specify which bits are set using CCmode macros?
> > I am not sure CC_MODE can solve the problem but I am not
> > entirely experienced with using different CC_MODEs, the first
> > thing that comes to mind is, how do you set the size of a
> > CCmode?
>
> Unfortunately undocumented, but UTSL, for example
> gcc/config/mips/mips-modes.def.
>
> If any register can be set to a "CC-value" then you don't need
> to set any specific set of registers aside.
>
Not any register, only the set of predicate registers we have. What's UTSL?
--
Paulo Matos