This is the mail archive of the
gcc@gcc.gnu.org
mailing list for the GCC project.
RE: Modeling predicate registers with more than one bit
- From: Hans-Peter Nilsson <hp at bitrange dot com>
- To: Paulo Matos <pmatos at broadcom dot com>
- Cc: "gcc at gcc dot gnu dot org" <gcc at gcc dot gnu dot org>
- Date: Tue, 26 Mar 2013 13:43:27 -0400 (EDT)
- Subject: RE: Modeling predicate registers with more than one bit
- References: <19EB96622A777C4AB91610E763265F461AE5A2 at SJEXCHMB14 dot corp dot ad dot broadcom dot com> <alpine dot BSF dot 2 dot 02 dot 1303042030210 dot 15765 at arjuna dot pair dot com> <19EB96622A777C4AB91610E763265F461B265E at SJEXCHMB14 dot corp dot ad dot broadcom dot com>
On Tue, 26 Mar 2013, Paulo Matos wrote:
> > -----Original Message-----
> > From: Hans-Peter Nilsson [mailto:hp@bitrange.com]
> > Sent: 05 March 2013 01:45
> > To: Paulo Matos
> > Cc: gcc@gcc.gnu.org
> > Subject: Re: Modeling predicate registers with more than one bit
> >
> > Except for CCmodes being dependent on source-modes, I'd sneak
> > peeks at PowerPC.
> >
>
> What do you mean by source modes?
The SI and HI in subsi3 and subhi3. IIRC you said your ISA set
CC-bits differently depending on the size of the operand.
> I am not sure CC_MODE can solve the problem but I am not
> entirely experienced with using different CC_MODEs, the first
> thing that comes to mind is, how do you set the size of a
> CCmode?
Unfortunately undocumented, but UTSL, for example
gcc/config/mips/mips-modes.def.
If any register can be set to a "CC-value" then you don't need
to set any specific set of registers aside.
brgds, H-P