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RE: Modeling predicate registers with more than one bit
- From: "Paulo Matos" <pmatos at broadcom dot com>
- To: "Hans-Peter Nilsson" <hp at bitrange dot com>
- Cc: "gcc at gcc dot gnu dot org" <gcc at gcc dot gnu dot org>
- Date: Tue, 26 Mar 2013 15:24:04 +0000
- Subject: RE: Modeling predicate registers with more than one bit
- References: <19EB96622A777C4AB91610E763265F461AE5A2 at SJEXCHMB14 dot corp dot ad dot broadcom dot com> <alpine dot BSF dot 2 dot 02 dot 1303042030210 dot 15765 at arjuna dot pair dot com>
Hi, sorry for the delay of this reply but just returned from paternity leave.
> -----Original Message-----
> From: Hans-Peter Nilsson [mailto:hp@bitrange.com]
> Sent: 05 March 2013 01:45
> To: Paulo Matos
> Cc: gcc@gcc.gnu.org
> Subject: Re: Modeling predicate registers with more than one bit
>
> Except for CCmodes being dependent on source-modes, I'd sneak
> peeks at PowerPC.
>
What do you mean by source modes?
> > If not, is there any way to currently
> > (as of HEAD) model this in GCC?
>
> IIUC, this sounds simply like having multiple separate
> condition-code registers, just with a size-dependent CCmodes
> twist; for each type of comparison where there'd be a separate
> CCmode variant, you also need separate CCmodes for each source
> mode M, all separated in cbranchM4 and cstoreM4.
>
I am not sure CC_MODE can solve the problem but I am not entirely experienced with using different CC_MODEs, the first thing that comes to mind is, how do you set the size of a CCmode?
A predicate register in our backend can be set as if it had different sizes. So, even though the register has 8 bits. It's possible to have just 1 bit set, 2 bit sets, 4 bit sets of 8 bits sets depending if a comparison is of mode BI, QI, SI or DI.
I might have to use proper registers like SH does (following Oleg suggestion).
Thanks,
Paulo Matos