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Re: MIPS & register allocation question

From: Steve Ellcey <steve dot ellcey at imgtec dot com>
To: Richard Sandiford <rdsandiford at googlemail dot com>
Cc: Steve Ellcey <sellcey at imgtec dot com>, <gcc at gcc dot gnu dot org>, <rsandiford at googlemail dot com>
Date: Wed, 27 Feb 2013 16:06:33 -0800
Subject: Re: MIPS & register allocation question
References: <22755512-7126-4a81-b7c0-3ae87b5f2678@BAMAIL02.ba.imgtec.org> <87ip5de6iv.fsf@talisman.default>

On Wed, 2013-02-27 at 22:28 +0000, Richard Sandiford wrote:

> FWIW, after seeing that, I tried the patch below.  Disabling
> ADJUST_REG_ALLOC_ORDER seemed to be a very mixed bag sizewise though --
> certainly not the consistent win that I hoped -- and I wasn't set up to
> do proper speed testing.  In the end I'm afraid I just let it drop.
> 
> Thanks,
> Richard

I'll try your patch on some of my benchmarks and see what happens.
One interesting thing I have noticed (sizewise) is that not using t0-t7
at all in MIPS16 code resulted in a code size reduction of around 1%.

Steve Ellcey

Follow-Ups:
- Re: MIPS & register allocation question
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References:
- MIPS & register allocation question
  - From: Steve Ellcey
- Re: MIPS & register allocation question
  - From: Richard Sandiford

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