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Re: Problem with branch delay slot
- From: Eric Botcazou <ebotcazou at adacore dot com>
- To: Jan Tlatlik <jantlatlik at gmail dot com>
- Cc: gcc at gcc dot gnu dot org
- Date: Fri, 21 Sep 2012 16:56:47 +0200
- Subject: Re: Problem with branch delay slot
- References: <CAF+9Wk9OdOUgRyEghnBsv25=jtK3ABD0DL-E9Xx3-gR32x=CCA@mail.gmail.com> <CAF+9Wk8Pv63ErsU=FnRz9htTjCbdagu8qyXCS+f_drQY+Uec7A@mail.gmail.com>
> I'm currently trying to retarget the gcc backend to a VLIW architecture
> developed in my workgroup.
> This architecture has a branch delay slot, so i tried the following
> (according to http://gcc.gnu.org/onlinedocs/gccint/Delay-Slots.html):
> (define_attr "type" "branch,other" (const_string "other"))
> (define_delay (eq_attr "type" "branch")
> [(eq_attr "type" "other") (nil) (nil)]
> (define_insn "call"
> [(call (match_operand:QI 0 "memory_operand" "")
> (match_operand:SI 1 "const_int_operand" ""))]
> "c7 brl %0"
> [(set_attr "type" "branch")]
> Unfortunately, the delay slot seems not to be used by the compiler. Even
> worse, there are no nops being emitted, which results in wrong asm code.
The delay slot isn't filled unless you enable optimization. In any case, the
nops are never emitted by the middle-end, it's up to the back-end to do it in
its TARGET_PRINT_OPERAND routine.
See the canonical examples of architectures with delay slots (SPARC, MIPS).