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RE: Expanding instructions with condition codes inter-deps
- From: <Paul_Koning at Dell dot com>
- To: <rth at redhat dot com>, <paulo at matos-sorge dot com>
- Cc: <gcc at gcc dot gnu dot org>
- Date: Tue, 18 Oct 2011 19:48:52 -0500
- Subject: RE: Expanding instructions with condition codes inter-deps
- References: <j7h191$hnc$1@dough.gmane.org> <4E9E0775.3020303@redhat.com>
>From: gcc-owner@gcc.gnu.org [mailto:gcc-owner@gcc.gnu.org] On Behalf Of Richard Henderson
>On 10/17/2011 03:50 AM, Paulo J. Matos wrote:
>>...
>> (for example, it would be ok to output negqi2, xorqi3 and
>> addc_internal since xorqi3 only sets N and Z, not the Carry bit)
>
>For that you'd have to model all of the flags bits independently.
>I don't believe any target has found that level of complexity to be worth the trouble.
Something like that shows up in the pdp11, where "mov" does not touch C. And C matters for multi-word arithmetic, and also for unsigned compares. So I think a CCmode implementation there would model C separately from the other three flag bits. So not 4 separate elements but two. Right now it's a cc0 target but I figure on changing that at some point. The reasons Paulo mentioned are one of the main reasons for that.
paul