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Re: i370 port
- From: "Paul Edwards" <mutazilah at gmail dot com>
- To: "Ulrich Weigand" <uweigand at de dot ibm dot com>
- Cc: <gcc at gcc dot gnu dot org>
- Date: Sat, 20 Aug 2011 20:08:09 +1000
- Subject: Re: i370 port
And here is the same debug info as last time ...
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include "rtl.h"
rtx
foo (rtx addr, int size, int n_refs)
{
int offset = 0;
switch (GET_CODE (addr))
{
case PRE_INC:
offset = (n_refs + 1) * size;
break;
case PRE_DEC:
offset = -(n_refs + 1) * size;
break;
case POST_INC:
offset = n_refs * size;
break;
}
if (offset)
addr = gen_rtx_PLUS (GET_MODE (addr), XEXP (addr, 0),
GEN_INT (offset));
else
addr = XEXP (addr, 0);
return addr;
}
COPY PDPTOP
CSECT
* Program text area
DS 0F
* X-func foo prologue
FOO PDPPRLG CINDEX=0,FRAME=120,BASER=12,ENTRY=YES
B FEN0
LTORG
FEN0 EQU *
DROP 12
BALR 12,0
USING *,12
PG0 EQU *
LR 11,1
L 10,=A(PGT0)
* Function foo code
MVC 112(8,13),=F'0'
SLR 8,8
SLR 9,9
LR 6,8
LR 7,9
L 3,0(11)
L 2,8(11)
LH 4,0(3)
N 4,=XL4'0000FFFF'
ST 4,104(13)
LA 5,110(0,0)
CLR 4,5
BE L3
BH L6
LA 15,109(0,0)
CLR 4,15
BE L4
B L7
L6 EQU *
L 5,104(13)
LA 4,112(0,0)
CLR 5,4
BE L5
B L7
L3 EQU *
A 2,=F'1'
L 15,4(11)
ST 15,116(13)
L 4,112(13)
L 5,4+112(13)
MR 4,2
ST 4,112(13)
ST 5,4+112(13)
LR 2,5
B L2
L4 EQU *
X 2,=F'-1'
L 9,4(11)
MR 8,2
LR 2,9
B L2
L5 EQU *
L 7,4(11)
MR 6,2
LR 2,7
L2 EQU *
LTR 2,2
BE L7
MVC 88(4,13),=F'0'
ST 2,92(13)
LA 1,88(,13)
L 15,=V(ZZZ@947)
BALR 14,15
MVC 88(4,13),=F'88'
SLR 5,5
IC 5,2(3)
ST 5,92(13)
MVC 96(4,13),4(3)
ST 15,100(13)
LA 1,88(,13)
L 15,=V(ZZZ@957)
BALR 14,15
LR 3,15
B L8
L7 EQU *
L 3,4(3)
L8 EQU *
LR 15,3
* Function foo epilogue
PDPEPIL
* Function foo literal pool
DS 0F
LTORG
* Function foo page table
DS 0F
PGT0 EQU *
DC A(PG0)
END
;; Function foo
;; 8 regs to allocate: 37 28 29 31 (2) 35 (2) 34 (2) 26 27
;; 26 conflicts: 26 27 28 29 31 34 35 37 11 15
;; 27 conflicts: 26 27 28 31 34 35 37 11
;; 28 conflicts: 26 27 28 31 34 35 37 11
;; 29 conflicts: 26 29 11
;; 31 conflicts: 26 27 28 31 34 35 37 11
;; 34 conflicts: 26 27 28 31 34 35 37 11
;; 35 conflicts: 26 27 28 31 34 35 37 11
;; 37 conflicts: 26 27 28 31 34 35 37 11
Spilling for insn 3.
Spilling for insn 4.
Spilling for insn 5.
Spilling for insn 45.
Spilling for insn 46.
Using reg 15 for reload 0
Spilling for insn 48.
Using reg 4 for reload 0
Spilling for insn 50.
Using reg 4 for reload 0
Spilling for insn 55.
Using reg 4 for reload 0
Spilling for insn 19.
Spilling for insn 29.
Spilling for insn 37.
Spilling for insn 63.
Spilling for insn 64.
Spilling for insn 67.
Spilling for insn 71.
Using reg 2 for reload 0
Spilling for insn 72.
Spilling for insn 73.
Spilling for insn 80.
Register 37 now on stack.
Spilling for insn 3.
Spilling for insn 4.
Spilling for insn 5.
Spilling for insn 45.
Using reg 15 for reload 0
Spilling for insn 46.
Using reg 15 for reload 1
Using reg 4 for reload 0
Spilling for insn 48.
Using reg 4 for reload 1
Using reg 5 for reload 0
Spilling for insn 50.
Using reg 4 for reload 1
Using reg 5 for reload 0
Spilling for insn 55.
Using reg 4 for reload 1
Using reg 5 for reload 0
Spilling for insn 19.
Spilling for insn 29.
Spilling for insn 37.
Spilling for insn 63.
Spilling for insn 64.
Spilling for insn 67.
Spilling for insn 71.
Using reg 2 for reload 0
Spilling for insn 72.
Spilling for insn 73.
Spilling for insn 80.
Register 31 now on stack.
Spilling for insn 113.
Spilling for insn 3.
Spilling for insn 4.
Spilling for insn 5.
Spilling for insn 45.
Using reg 4 for reload 0
Spilling for insn 46.
Using reg 4 for reload 1
Using reg 5 for reload 0
Spilling for insn 48.
Using reg 4 for reload 1
Using reg 5 for reload 0
Spilling for insn 50.
Using reg 4 for reload 1
Using reg 5 for reload 0
Spilling for insn 55.
Using reg 4 for reload 1
Using reg 5 for reload 0
Spilling for insn 19.
Using reg 4 for reload 0
Spilling for insn 20.
Using reg 4 for reload 0
Spilling for insn 21.
Spilling for insn 29.
Spilling for insn 37.
Spilling for insn 63.
Spilling for insn 64.
Spilling for insn 67.
Spilling for insn 71.
Using reg 2 for reload 0
Spilling for insn 72.
Spilling for insn 73.
Spilling for insn 80.
Reloads for insn # 113
Reload 0: reload_out (DI) = (reg:DI 31 [ size ])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (reg:DI 31 [ size ])
Reloads for insn # 3
Reload 0: reload_in (SI) = (mem/f:SI (reg/f:SI 11 11) [2 addr+0 S4 A32])
DATA_REGS, RELOAD_FOR_INPUT (opnum = 1), optional
reload_in_reg: (mem/f:SI (reg/f:SI 11 11) [2 addr+0 S4 A32])
Reloads for insn # 5
Reload 0: reload_in (SI) = (mem/f:SI (plus:SI (reg/f:SI 11 11)
(const_int 8 [0x8]))
[3 n_refs+0 S4 A32])
DATA_REGS, RELOAD_FOR_INPUT (opnum = 1), optional
reload_in_reg: (mem/f:SI (plus:SI (reg/f:SI 11 11)
(const_int 8 [0x8]))
[3 n_refs+0 S4 A32])
Reloads for insn # 45
Reload 0: reload_in (HI) = (mem/s:HI (reg/v/f:SI 3 3 [orig:26 addr ] [26])
[4 S2 A32])
reload_out (SI) = (reg:SI 37)
DATA_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (mem/s:HI (reg/v/f:SI 3 3 [orig:26 addr ] [26]) [4
S2 A32])
reload_out_reg: (reg:SI 37)
reload_reg_rtx: (reg:SI 4 4)
Reloads for insn # 46
Reload 0: reload_in (SI) = (reg:SI 37)
DATA_REGS, RELOAD_FOR_INPUT (opnum = 0)
reload_in_reg: (reg:SI 37)
reload_reg_rtx: (reg:SI 4 4)
Reload 1: reload_in (SI) = (const_int 110 [0x6e])
ADDR_REGS, RELOAD_FOR_INPUT (opnum = 1)
reload_in_reg: (const_int 110 [0x6e])
reload_reg_rtx: (reg:SI 5 5)
Reloads for insn # 48
Reload 0: reload_in (SI) = (reg:SI 37)
DATA_REGS, RELOAD_FOR_INPUT (opnum = 0)
reload_in_reg: (reg:SI 37)
reload_reg_rtx: (reg:SI 4 4)
Reload 1: reload_in (SI) = (const_int 110 [0x6e])
ADDR_REGS, RELOAD_FOR_INPUT (opnum = 1)
reload_in_reg: (const_int 110 [0x6e])
reload_reg_rtx: (reg:SI 5 5)
Reloads for insn # 50
Reload 0: reload_in (SI) = (reg:SI 37)
DATA_REGS, RELOAD_FOR_INPUT (opnum = 0)
reload_in_reg: (reg:SI 37)
reload_reg_rtx: (reg:SI 4 4)
Reload 1: reload_in (SI) = (const_int 109 [0x6d])
ADDR_REGS, RELOAD_FOR_INPUT (opnum = 1)
reload_in_reg: (const_int 109 [0x6d])
reload_reg_rtx: (reg:SI 15 15)
Reloads for insn # 55
Reload 0: reload_in (SI) = (reg:SI 37)
DATA_REGS, RELOAD_FOR_INPUT (opnum = 0)
reload_in_reg: (reg:SI 37)
reload_reg_rtx: (reg:SI 5 5)
Reload 1: reload_in (SI) = (const_int 112 [0x70])
ADDR_REGS, RELOAD_FOR_INPUT (opnum = 1)
reload_in_reg: (const_int 112 [0x70])
reload_reg_rtx: (reg:SI 4 4)
Reloads for insn # 19
Reload 0: reload_out (SI) = (subreg:SI (reg:DI 31 [ size ]) 4)
DATA_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
reload_out_reg: (subreg:SI (reg:DI 31 [ size ]) 4)
reload_reg_rtx: (reg:SI 15 15)
Reload 1: reload_in (SI) = (reg/v:SI 27 [ size ])
DATA_REGS, RELOAD_FOR_INPUT (opnum = 1), optional
reload_in_reg: (reg/v:SI 27 [ size ])
Reloads for insn # 20
Reload 0: reload_in (DI) = (reg:DI 31 [ size ])
reload_out (DI) = (reg:DI 31 [ size ])
DATA_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg:DI 31 [ size ])
reload_out_reg: (reg:DI 31 [ size ])
reload_reg_rtx: (reg:DI 4 4)
Reloads for insn # 21
Reload 0: reload_in (SI) = (subreg:SI (reg:DI 31 [ size ]) 4)
DATA_REGS, RELOAD_FOR_INPUT (opnum = 1)
reload_in_reg: (subreg:SI (reg:DI 31 [ size ]) 4)
reload_reg_rtx: (reg:SI 5 5)
Reloads for insn # 29
Reload 0: reload_in (SI) = (reg/v:SI 27 [ size ])
DATA_REGS, RELOAD_FOR_INPUT (opnum = 1), optional
reload_in_reg: (reg/v:SI 27 [ size ])
Reloads for insn # 37
Reload 0: reload_in (SI) = (reg/v:SI 27 [ size ])
DATA_REGS, RELOAD_FOR_INPUT (opnum = 1), optional
reload_in_reg: (reg/v:SI 27 [ size ])
Reloads for insn # 63
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
Reloads for insn # 64
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
DATA_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
Reloads for insn # 67
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
Reloads for insn # 71
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
DATA_REGS, RELOAD_OTHER (opnum = 0)
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
reload_reg_rtx: (reg:SI 5 5)
Reloads for insn # 72
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 96
[0x60])) [0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 96
[0x60])) [0 S4 A32])
Reloads for insn # 73
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 100
[0x64])) [0 S4 A32])
DATA_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 100
[0x64])) [0 S4 A32])
Reloads for insn # 80
Reload 0: reload_in (SI) = (mem/s:SI (plus:SI (reg/v/f:SI 3 3 [orig:26
addr ] [26])
(const_int 4 [0x4]))
[0 <variable>.rtx+0 S4 A32])
DATA_REGS, RELOAD_FOR_INPUT (opnum = 1), optional
reload_in_reg: (mem/s:SI (plus:SI (reg/v/f:SI 3 3 [orig:26 addr ]
[26])
(const_int 4 [0x4]))
[0 <variable>.rtx+0 S4 A32])
;; Register dispositions:
26 in 3 28 in 2 29 in 2 34 in 8 35 in 6
;; Hard regs used: 2 3 4 5 6 7 8 9 11 13 15
(note 2 0 96 NOTE_INSN_DELETED)
;; Start of basic block 0, registers live: 11 [11] 13 [13]
(note 96 2 113 0 [bb 0] NOTE_INSN_BASIC_BLOCK)
(insn 113 96 114 0 (set (mem:DI (plus:SI (reg/f:SI 13 13)
(const_int 112 [0x70])) [22 S8 A8])
(const_int 0 [0x0])) 13 {*i370.md:786} (nil)
(nil))
(insn 114 113 115 0 (set (reg:DI 8 8 [orig:34 size ] [34])
(const_int 0 [0x0])) 13 {*i370.md:786} (nil)
(nil))
(insn 115 114 3 0 (set (reg:DI 6 6 [orig:35 size ] [35])
(const_int 0 [0x0])) 13 {*i370.md:786} (nil)
(nil))
(insn 3 115 4 0 (set (reg/v/f:SI 3 3 [orig:26 addr ] [26])
(mem/f:SI (reg/f:SI 11 11) [2 addr+0 S4 A32])) 15 {movsi} (nil)
(expr_list:REG_EQUIV (mem/f:SI (reg/f:SI 11 11) [2 addr+0 S4 A32])
(nil)))
(note 4 3 5 0 NOTE_INSN_DELETED)
(insn 5 4 6 0 (set (reg/v:SI 2 2 [orig:28 n_refs ] [28])
(mem/f:SI (plus:SI (reg/f:SI 11 11)
(const_int 8 [0x8])) [3 n_refs+0 S4 A32])) 15 {movsi} (nil)
(expr_list:REG_EQUIV (mem/f:SI (plus:SI (reg/f:SI 11 11)
(const_int 8 [0x8])) [3 n_refs+0 S4 A32])
(nil)))
(note 6 5 44 0 NOTE_INSN_FUNCTION_BEG)
(note 44 6 117 0 NOTE_INSN_DELETED)
(insn 117 44 45 0 alias.c:15 (set (reg:HI 4 4)
(mem/s:HI (reg/v/f:SI 3 3 [orig:26 addr ] [26]) [4 S2 A32])) 16
{*i370.md:1004} (nil)
(nil))
(insn 45 117 118 0 alias.c:15 (set (reg:SI 4 4)
(zero_extend:SI (reg:HI 4 4))) 30 {zero_extendhisi2} (insn_list 3
(nil))
(nil))
(insn 118 45 119 0 alias.c:15 (set (mem:SI (plus:SI (reg/f:SI 13 13)
(const_int 104 [0x68])) [21 S4 A8])
(reg:SI 4 4)) 15 {movsi} (nil)
(nil))
(insn 119 118 46 0 alias.c:15 (set (reg:SI 5 5)
(const_int 110 [0x6e])) 15 {movsi} (nil)
(nil))
(insn:QI 46 119 47 0 alias.c:15 (set (cc0)
(compare (reg:SI 4 4)
(reg:SI 5 5))) 5 {cmpsi} (insn_list 45 (nil))
(nil))
(jump_insn 47 46 97 0 alias.c:15 (set (pc)
(if_then_else (eq (cc0)
(const_int 0 [0x0]))
(label_ref 16)
(pc))) 104 {beq} (nil)
(expr_list:REG_BR_PROB (const_int 2900 [0xb54])
(nil)))
;; End of basic block 0, registers live:
11 [11] 13 [13] 26 27 28 31 34 35 37
;; Start of basic block 1, registers live: 11 [11] 13 [13] 26 27 28 34 35 37
(note 97 47 48 1 [bb 1] NOTE_INSN_BASIC_BLOCK)
(insn:QI 48 97 49 1 alias.c:15 (set (cc0)
(compare (reg:SI 4 4)
(reg:SI 5 5))) 5 {cmpsi} (nil)
(nil))
(jump_insn 49 48 98 1 alias.c:15 (set (pc)
(if_then_else (gtu (cc0)
(const_int 0 [0x0]))
(label_ref 54)
(pc))) 107 {bgtu} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 1, registers live:
11 [11] 13 [13] 26 27 28 34 35 37
;; Start of basic block 2, registers live: 11 [11] 13 [13] 26 27 28 34 37
(note 98 49 120 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 120 98 50 2 alias.c:15 (set (reg:SI 15 15)
(const_int 109 [0x6d])) 15 {movsi} (nil)
(nil))
(insn:QI 50 120 51 2 alias.c:15 (set (cc0)
(compare (reg:SI 4 4)
(reg:SI 15 15))) 5 {cmpsi} (nil)
(nil))
(jump_insn 51 50 99 2 alias.c:15 (set (pc)
(if_then_else (eq (cc0)
(const_int 0 [0x0]))
(label_ref 25)
(pc))) 104 {beq} (nil)
(expr_list:REG_BR_PROB (const_int 2900 [0xb54])
(nil)))
;; End of basic block 2, registers live:
11 [11] 13 [13] 26 27 28 34
;; Start of basic block 3, registers live: 11 [11] 13 [13] 26
(note 99 51 52 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(jump_insn 52 99 53 3 alias.c:15 (set (pc)
(label_ref 78)) 126 {jump} (nil)
(nil))
;; End of basic block 3, registers live:
11 [11] 13 [13] 26
(barrier 53 52 54)
;; Start of basic block 4, registers live: 11 [11] 13 [13] 26 27 28 35 37
(code_label 54 53 100 4 6 "" [1 uses])
(note 100 54 121 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(insn 121 100 122 4 alias.c:15 (set (reg:SI 5 5)
(mem:SI (plus:SI (reg/f:SI 13 13)
(const_int 104 [0x68])) [21 S4 A8])) 15 {movsi} (nil)
(nil))
(insn 122 121 55 4 alias.c:15 (set (reg:SI 4 4)
(const_int 112 [0x70])) 15 {movsi} (nil)
(nil))
(insn:QI 55 122 56 4 alias.c:15 (set (cc0)
(compare (reg:SI 5 5)
(reg:SI 4 4))) 5 {cmpsi} (nil)
(nil))
(jump_insn 56 55 101 4 alias.c:15 (set (pc)
(if_then_else (eq (cc0)
(const_int 0 [0x0]))
(label_ref 35)
(pc))) 104 {beq} (nil)
(expr_list:REG_BR_PROB (const_int 2900 [0xb54])
(nil)))
;; End of basic block 4, registers live:
11 [11] 13 [13] 26 27 28 35
;; Start of basic block 5, registers live: 11 [11] 13 [13] 26
(note 101 56 57 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
(jump_insn 57 101 58 5 alias.c:15 (set (pc)
(label_ref 78)) 126 {jump} (nil)
(nil))
;; End of basic block 5, registers live:
11 [11] 13 [13] 26
(barrier 58 57 16)
;; Start of basic block 6, registers live: 11 [11] 13 [13] 26 27 28 31
(code_label 16 58 102 6 3 "" [1 uses])
(note 102 16 17 6 [bb 6] NOTE_INSN_BASIC_BLOCK)
(note 17 102 18 6 ("alias.c") 15)
(insn 18 17 19 6 alias.c:15 (set (reg/v:SI 2 2 [orig:28 n_refs ] [28])
(plus:SI (reg/v:SI 2 2 [orig:28 n_refs ] [28])
(const_int 1 [0x1]))) 41 {addsi3} (nil)
(nil))
(insn 19 18 123 6 alias.c:15 (set (reg:SI 15 15)
(mem/f:SI (plus:SI (reg/f:SI 11 11)
(const_int 4 [0x4])) [3 size+0 S4 A32])) 15 {movsi} (nil)
(nil))
(insn 123 19 124 6 alias.c:15 (set (mem:SI (plus:SI (reg/f:SI 13 13)
(const_int 116 [0x74])) [22 S4 A8])
(reg:SI 15 15)) 15 {movsi} (nil)
(nil))
(insn 124 123 20 6 alias.c:15 (set (reg:DI 4 4)
(mem:DI (plus:SI (reg/f:SI 13 13)
(const_int 112 [0x70])) [22 S8 A8])) 13 {*i370.md:786} (nil)
(nil))
(insn 20 124 125 6 alias.c:15 (set (reg:DI 4 4)
(mult:DI (reg:DI 4 4)
(reg/v:SI 2 2 [orig:28 n_refs ] [28]))) 53 {*i370.md:2604}
(insn_list 18 (insn_list 19 (nil)))
(nil))
(insn 125 20 21 6 alias.c:15 (set (mem:DI (plus:SI (reg/f:SI 13 13)
(const_int 112 [0x70])) [22 S8 A8])
(reg:DI 4 4)) 13 {*i370.md:786} (nil)
(nil))
(insn 21 125 22 6 alias.c:15 (set (reg/v:SI 2 2 [orig:29 offset ] [29])
(reg:SI 5 5)) 15 {movsi} (insn_list 20 (nil))
(expr_list:REG_EQUAL (mult:SI (reg:SI 30)
(mem/f:SI (plus:SI (reg/f:SI 11 11)
(const_int 4 [0x4])) [3 size+0 S4 A32]))
(nil)))
(note 22 21 23 6 ("alias.c") 16)
(jump_insn 23 22 24 6 alias.c:16 (set (pc)
(label_ref 43)) 126 {jump} (nil)
(nil))
;; End of basic block 6, registers live:
11 [11] 13 [13] 26 29
(barrier 24 23 25)
;; Start of basic block 7, registers live: 11 [11] 13 [13] 26 27 28 34
(code_label 25 24 103 7 4 "" [1 uses])
(note 103 25 26 7 [bb 7] NOTE_INSN_BASIC_BLOCK)
(note 26 103 27 7 ("alias.c") 18)
(note 27 26 28 7 NOTE_INSN_DELETED)
(insn 28 27 29 7 alias.c:18 (set (reg/v:SI 2 2 [orig:28 n_refs ] [28])
(not:SI (reg/v:SI 2 2 [orig:28 n_refs ] [28]))) 86 {*i370.md:3685}
(nil)
(nil))
(insn 29 28 30 7 alias.c:18 (set (reg:SI 9 9 [orig:34 size+4 ] [34])
(mem/f:SI (plus:SI (reg/f:SI 11 11)
(const_int 4 [0x4])) [3 size+0 S4 A32])) 15 {movsi} (nil)
(nil))
(insn 30 29 31 7 alias.c:18 (set (reg:DI 8 8 [orig:34 size ] [34])
(mult:DI (reg:DI 8 8 [orig:34 size ] [34])
(reg/v:SI 2 2 [orig:28 n_refs ] [28]))) 53 {*i370.md:2604}
(insn_list 28 (insn_list 29 (nil)))
(nil))
(insn 31 30 32 7 alias.c:18 (set (reg/v:SI 2 2 [orig:29 offset ] [29])
(reg:SI 9 9 [orig:34 size+4 ] [34])) 15 {movsi} (insn_list 30 (nil))
(expr_list:REG_EQUAL (mult:SI (reg:SI 33)
(mem/f:SI (plus:SI (reg/f:SI 11 11)
(const_int 4 [0x4])) [3 size+0 S4 A32]))
(nil)))
(note 32 31 33 7 ("alias.c") 19)
(jump_insn 33 32 34 7 alias.c:19 (set (pc)
(label_ref 43)) 126 {jump} (nil)
(nil))
;; End of basic block 7, registers live:
11 [11] 13 [13] 26 29
(barrier 34 33 35)
;; Start of basic block 8, registers live: 11 [11] 13 [13] 26 27 28 35
(code_label 35 34 104 8 5 "" [1 uses])
(note 104 35 36 8 [bb 8] NOTE_INSN_BASIC_BLOCK)
(note 36 104 37 8 ("alias.c") 21)
(insn 37 36 38 8 alias.c:21 (set (reg:SI 7 7 [orig:35 size+4 ] [35])
(mem/f:SI (plus:SI (reg/f:SI 11 11)
(const_int 4 [0x4])) [3 size+0 S4 A32])) 15 {movsi} (nil)
(nil))
(insn 38 37 39 8 alias.c:21 (set (reg:DI 6 6 [orig:35 size ] [35])
(mult:DI (reg:DI 6 6 [orig:35 size ] [35])
(reg/v:SI 2 2 [orig:28 n_refs ] [28]))) 53 {*i370.md:2604}
(insn_list 37 (nil))
(nil))
(insn 39 38 40 8 alias.c:21 (set (reg/v:SI 2 2 [orig:29 offset ] [29])
(reg:SI 7 7 [orig:35 size+4 ] [35])) 15 {movsi} (insn_list 38 (nil))
(expr_list:REG_EQUAL (mult:SI (reg/v:SI 2 2 [orig:28 n_refs ] [28])
(mem/f:SI (plus:SI (reg/f:SI 11 11)
(const_int 4 [0x4])) [3 size+0 S4 A32]))
(nil)))
;; End of basic block 8, registers live:
11 [11] 13 [13] 26 29
(note 40 39 43 ("alias.c") 22)
;; Start of basic block 9, registers live: 11 [11] 13 [13] 26 29
(code_label 43 40 105 9 2 "" [2 uses])
(note 105 43 60 9 [bb 9] NOTE_INSN_BASIC_BLOCK)
(insn:QI 60 105 61 9 alias.c:22 (set (cc0)
(reg/v:SI 2 2 [orig:29 offset ] [29])) 1 {tstsi} (nil)
(nil))
(jump_insn 61 60 106 9 alias.c:22 (set (pc)
(if_then_else (eq (cc0)
(const_int 0 [0x0]))
(label_ref 78)
(pc))) 104 {beq} (nil)
(expr_list:REG_BR_PROB (const_int 7000 [0x1b58])
(nil)))
;; End of basic block 9, registers live:
11 [11] 13 [13] 26 29
;; Start of basic block 10, registers live: 11 [11] 13 [13] 26 29
(note 106 61 63 10 [bb 10] NOTE_INSN_BASIC_BLOCK)
(insn 63 106 64 10 alias.c:22 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88 [0x58])) [0 S4 A32])
(const_int 0 [0x0])) 15 {movsi} (nil)
(nil))
(insn 64 63 65 10 alias.c:22 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92 [0x5c])) [0 S4 A32])
(reg/v:SI 2 2 [orig:29 offset ] [29])) 15 {movsi} (nil)
(nil))
(call_insn 65 64 66 10 alias.c:22 (set (reg:SI 15 15)
(call (mem:QI (symbol_ref/v:SI ("ZZZ_947") [flags 0x41]
<function_decl c8c000 ZZZ_947>) [0 S1 A8])
(const_int 8 [0x8]))) 132 {*i370.md:4869} (nil)
(nil)
(nil))
(note 66 65 67 10 NOTE_INSN_DELETED)
(insn 67 66 68 10 alias.c:22 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88 [0x58])) [0 S4 A32])
(const_int 88 [0x58])) 15 {movsi} (nil)
(nil))
(note 68 67 69 10 NOTE_INSN_DELETED)
(note 69 68 70 10 NOTE_INSN_DELETED)
(note 70 69 71 10 NOTE_INSN_DELETED)
(insn 71 70 126 10 alias.c:22 (set (reg:SI 5 5)
(zero_extend:SI (mem/s:QI (plus:SI (reg/v/f:SI 3 3 [orig:26 addr ]
[26])
(const_int 2 [0x2])) [4 S1 A16]))) 31 {zero_extendqisi2}
(nil)
(nil))
(insn 126 71 72 10 alias.c:22 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92 [0x5c])) [0 S4 A32])
(reg:SI 5 5)) 15 {movsi} (nil)
(nil))
(insn 72 126 73 10 alias.c:22 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 96 [0x60])) [0 S4 A32])
(mem/s:SI (plus:SI (reg/v/f:SI 3 3 [orig:26 addr ] [26])
(const_int 4 [0x4])) [0 <variable>.rtx+0 S4 A32])) 15
{movsi} (nil)
(nil))
(insn 73 72 74 10 alias.c:22 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 100 [0x64])) [0 S4 A32])
(reg:SI 15 15)) 15 {movsi} (insn_list 65 (nil))
(nil))
(call_insn 74 73 75 10 alias.c:22 (set (reg:SI 15 15)
(call (mem:QI (symbol_ref/v:SI ("ZZZ_957") [flags 0x41]
<function_decl c63af8 ZZZ_957>) [0 S1 A8])
(const_int 16 [0x10]))) 132 {*i370.md:4869} (nil)
(nil)
(nil))
(insn 75 74 76 10 alias.c:22 (set (reg/v/f:SI 3 3 [orig:26 addr ] [26])
(reg:SI 15 15)) 15 {movsi} (insn_list 74 (nil))
(nil))
(jump_insn 76 75 77 10 alias.c:22 (set (pc)
(label_ref 81)) 126 {jump} (nil)
(nil))
;; End of basic block 10, registers live:
11 [11] 13 [13] 26
(barrier 77 76 78)
;; Start of basic block 11, registers live: 11 [11] 13 [13] 26
(code_label 78 77 107 11 7 "" [3 uses])
(note 107 78 80 11 [bb 11] NOTE_INSN_BASIC_BLOCK)
(insn 80 107 81 11 alias.c:22 (set (reg/v/f:SI 3 3 [orig:26 addr ] [26])
(mem/s:SI (plus:SI (reg/v/f:SI 3 3 [orig:26 addr ] [26])
(const_int 4 [0x4])) [0 <variable>.rtx+0 S4 A32])) 15
{movsi} (nil)
(nil))
;; End of basic block 11, registers live:
11 [11] 13 [13] 26
;; Start of basic block 12, registers live: 11 [11] 13 [13] 26
(code_label 81 80 108 12 8 "" [1 uses])
(note 108 81 89 12 [bb 12] NOTE_INSN_BASIC_BLOCK)
(note 89 108 92 12 NOTE_INSN_FUNCTION_END)
(insn 92 89 95 12 alias.c:22 (set (reg/i:SI 15 15 [ <result> ])
(reg/v/f:SI 3 3 [orig:26 addr ] [26])) 15 {movsi} (nil)
(nil))
(insn 95 92 116 12 alias.c:22 (use (reg/i:SI 15 15 [ <result> ])) -1
(insn_list 92 (nil))
(nil))
;; End of basic block 12, registers live:
11 [11] 13 [13] 15 [15]
(note 116 95 0 NOTE_INSN_DELETED)