[Take 2] Help with specifying processor pipeline GCC4.5.1

[Rohit Arul Raj <rohitarulraj at gmail dot com>]

Hello All,

I need some help with setting the pipeline hazard recognizer (I am
working with gcc v4.5.1 for a private target).

A brief pipeline description of my target:

We have 2 functional units
? ? ? ?1) For multiplication.
? ? ? ?2) For All other instructions.

a) Multiply instructions are not pipelined.
b) It takes 4 cycles to execute a multiply instruction.
c) The result of multiply instruction will be available after 4 cycles.

So there should be a 4 cycle gap between 2 multiply instructions
(independent/dependent) and also its depend instructions (other than
multiply).

e.g.1:
? ? ? ?mult R3, R4, R5 -- (A)
? ? ? ?add ?R0, R1, R2
? ? ? ?mult R7, R8, R9 -- (B)

? ? ? ?A) & (B) are independent.
? ? ? ?This is a pipeline error.
? ? ? ?Need to add 2 NOP's or schedule 2 other independent
instructions before (B).

e.g.2:
? ? ? ?mult R3, R4, R5 ?--(A)
? ? ? ?add ?R7, R8, R9
? ? ? ?add ?R5, R1, R2 ?--(B)

? ? ? ?(A) & (B) are dependent.
? ? ? ?Even though there is no pipeline error, the value of "R5" used will
not be the updated one as 'mult' takes 4 cycles for the result to be
available.
? ? ? ?Need to add 2 NOP's or schedule 2 other independent
instructions before (B).

I have done the following, but not sure if this will take care of:

A) 4 cycle gap between 2 Independent multiply instructions
B) 4 cycle gap beween multiply and any other dependent instruction.

(define_automaton "pipeline")
(define_cpu_unit "simple" "pipeline")
(define_cpu_unit "mult" "pipeline")

(define_insn_reservation "any_insn" 1 (eq_attr "type" "!mul") "simple")
(define_insn_reservation "mult" 4 (eq_attr "type" "mul") "mult*4")


In case other independent instructions are not available to be
scheduled for this latency, i will be inserting NOP's from the
backend. But i want to make sure the correct info is passed to the
scheduler.

Any comments/suggestions?

Thanks,
Rohit