Re: Plus Reload

[Ian Lance Taylor <iant at google dot com>]

Gidi Nave <gidi.nave.1@gmail.com> writes:

> On Tue, Jan 11, 2011 at 7:22 PM, Ian Lance Taylor <iant@google.com> wrote:
>> Gidi Nave <gidi.nave.1@gmail.com> writes:
>>
>>> On Tue, Jan 11, 2011 at 5:34 PM, Ian Lance Taylor <iant@google.com> wrote:
>>>
>>>> So why doesn't d1 = d1 + -96 match the last instruction there?
>>>>
>>> because it's: Â Âadd d,d unsigned
>>> we don't have: Âadd d,d signed
>>>
>>> and in this case we need: d = r + (-96)
>>
>> Addition of signed and unsigned numbers is the same operation at the
>> machine level. ÂAre there limitations on the signed value? ÂIf so, is
>> there is a sub instruction?
>
> There are limitation for the signed value for D class registers.
> There is a sub instruction for D registers, but it's limited to U5
> (unsigned of 5 bits) which is not the case here.

Thanks.  Since we don't know the details of your processor, we could be
more helpful if you provided this sort of information up front.  It
sounds like you are saying that there is no way to subtract 96 without
using an extra register.  Is that correct?

If that is the case, then I agree with Jeff that you are going to need
to define a secondary reload.  Look at TARGET_SECONDARY_RELOAD in the
docs.

By the way, if the restrictions on addition (which you did not describe)
are less severe than the restrictions on subtraction, then you should
consider adjusting your frame pointer so that most stack slots are at a
positive offset rather than a negative one.  I don't know if that is
what is going on here, though a negative offset is certainly unusual.

Ian