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Re: combine two load insns
On Dec 8, 2010, at 11:37 AM, Jeff Law wrote:
> On 12/08/10 09:18, Frederic Riss wrote:
>>
>> OK, I see your point, but I tend to think the the odds of the register
>> allocator being able to coalesce the additional DI->SI moves in the
>> pre-IRA approach are by far higher that the odds of having merge
>> candidates after register allocation.
> I agree, but note that failure to coalesce leads to code quality regression.
>
> Also note that handling of double-word values is, IMHO, the allocator's biggest problem area. This has been greatly helped by Bernd's recent work, but there's still significant amounts of work to do here.
This probably has been discussed at length in the past, but as a relative newcomer I'll make this observation... I wonder how much is lost by GCC's insistence that multi-register values must be in adjacent registers. Obviously that's hard to change (the registers would have to be explicitly listed instead of implied by the first register number). And in some cases it is actually required. But in many cases, it's not (in some machines, never). And I would think that register allocation could benefit from not having such a restriction. The item in question here is just one example.
paul