Re: Dedicated logical instructions

["Radu Hobincu" <radu dot hobincu at arh dot pub dot ro>]

Thank you, that worked out eventually.

However, now I have another problem. I have 2 instructions in the ISA:
'where' and 'endwhere' which modify the behavior of the instructions put
in between them. I made a macro with inline assembly for each of them. The
problem is that since `endwhere` doesn't have any operands and doesn't
clobber any registers, the GCC optimization reorders it and places the
`endwhere` immediately after `where` leaving all the instructions outside
the block.

A hack-solution came in mind, and that is specifying that the asm inline
uses all the registers as operands without actually placing them in the
instruction mnemonic. The problem is I don't know how to write that
especially when I don't know the variables names (I want to use the same
macro in more than one place).


These are the macros:

#define WHERE(_condition)				\
	__asm__ __volatile__("move %0 %0, wherenz 0xf"	\
		:       				\
		: "v" (_condition)			\
		);

#define ENDWHERE                			\
	__asm__ __volatile__("nop, endwhere");



This is the C code:
vector doSmth(vector a, vector b){
	WHERE(LT(a, b))
	  a++;
	ENDWHERE
	return a;
}

And this is what cc1 -O3 outputs:

;# 113
"/home/rhobincu/svnroot/connex/trunk/software/gcc/examples/include/connex.h"
1
	lt R31 R16 R17
;# 4 "/home/rhobincu/svnroot/connex/trunk/software/gcc/examples/test0.c" 1
	move R31 R31, wherenz 0xf
;# 6 "/home/rhobincu/svnroot/connex/trunk/software/gcc/examples/test0.c" 1
	nop, endwhere
	iadd R31 R16 1

You can see that the `nop,endwhere` and the `iadd ...` insns are inverted.
I think this is similar to having instructions for enabling and disabling
interrupts: the instructions have no operands, but the compiler shouldn't
move the block in between them for optimization.

Thank you, and please, if I waste too much of your time with random
questions, tell me and I will stop. :)

Regards,
R.

> "Radu Hobincu" <radu.hobincu@arh.pub.ro> writes:
>
>> I have another, quick question: I have dedicated logical instructions
in
>> my RISC machine (lt - less than, gt - greater than, ult - unsigned less
than, etc.). I'm also working on adding instructions for logical OR, AND,
>> NOT, XOR. While reading GCC internals, I've stumbled on this:
>> "Except when they appear in the condition operand of a COND_EXPR,
logical
>> `and` and `or` operators are simplified as follows: a = b && c
>> becomes
>> T1 = (bool)b;
>> if (T1)
>>   T1 = (bool)c;
>> a = T1;"
>> I really, really don't want this. Is there any way I can define the
instructions in the .md file so the compiler generates code for
computing
>> a boolean expression without using branches (using these dedicated
insns)?
>
> That is the only correct way to implement && and || in C, C++, and other
similar languages.  The question you should be asking is whether gcc will
be able to put simple cases without side effects back together again.  The
answer is that, yes, it should be able to do that.
>
> You should not worry about this level of things when it comes to writing
your backend port.  Language level details like this are handled by the
frontend, not the backend.  When your port is working, come back to this
and make sure that you get the kind of code you want.
>
> Ian
>