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Re: Is it possible to port GCC backend to a architecture with very limited hard registers?
- From: Ian Lance Taylor <iant at google dot com>
- To: redriver jiang <jiang dot redriver at gmail dot com>
- Cc: gcc at gcc dot gnu dot org
- Date: Wed, 17 Mar 2010 11:10:22 -0700
- Subject: Re: Is it possible to port GCC backend to a architecture with very limited hard registers?
- References: <714984df1003170555m6d38cf46y2b916f52ef6fa3f0@mail.gmail.com>
redriver jiang <jiang.redriver@gmail.com> writes:
> Right now I attempts to port the GCC backend to a MCU with very
> limited hard registers: only one 8 bit ACC reg, one 16 bit base reg
> for addressing, one stats reg.
> I searched the GCC backend porting, and seems 68HC1X has the similar
> scene, but it use many "ram simulated" register. I wonder that if it
> is possbile to provided thislimited 3 register to GCC bankend, and let
> all 16bit(HImode), 32bit(SImode) operands spilled to stack.
It should be possible, though it owuld not be easy to resolve all the
reload issues. gcc will not generate particularly good code for such
a processor; you will see an awful lot of register shuffling.
Ian