Re: Is it possible to port GCC backend to a architecture with very limited hard registers?

[Dave Hudson <gcc at blueteddy dot net>]

We only had one real 8-bit accumulator on that port (the W register) which we did not expose the RA, instead exposing 32 "virtual" 8-bit registers from which we could construct 8, 16, 32 and 64-bit pairs.  The key to really good code generation was to aggresively split the larger pseudo-operations after reload and eliminate all possible redundancy.

The IP2k did have 2 offsettable address pointers though, one as a stack pointer and one as a data pointer which made the code much easier to manage (there was also one that wasn't offsettable and wasn't anywhere near as useful).  I can imagine that any code where there's only one address register is going to be very messy because it will be permenantly swapping  things in and out of it as things like register spills happen.


Cheers,
Dave


On 17 Mar 2010, at 14:01, Alan Lehotsky wrote:

> Almost certainly you will run into severe problems in the reload phase.
> 
> You might also profitably study the ip2k port.  This is a ALU machine, but it does have multiple
> address registers.
> 
> 
> -----Original Message-----
>> From: redriver jiang <jiang.redriver@gmail.com>
>> Sent: Mar 17, 2010 8:55 AM
>> To: gcc@gcc.gnu.org
>> Subject: Is it possible to port GCC backend to a architecture with very  	limited hard registers?
>> 
>> Hi all,
>> 
>> Right now I attempts to port the GCC backend to a MCU with very
>> limited hard registers: only one 8 bit ACC reg, one 16 bit base reg
>> for addressing, one stats reg.
>> I searched the GCC backend porting, and seems 68HC1X has the similar
>> scene, but it use many "ram simulated" register. I wonder that if it
>> is possbile to provided thislimited 3 register to GCC bankend, and let
>> all 16bit(HImode), 32bit(SImode) operands spilled to stack.
>> 
>> Thanks!
>> 
>> Redriver
>