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On 12/21/2009 08:10 PM, Richard Henderson wrote:(define_insn_and_split "*cmp" [(set (match_operand:SI 0 "register_operand" "=r") (lt:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "register_operand" "r")))] "" "cmp %0,%1,%2\;andi $0,$0,1" "" [(set (match_dup 0) (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_CMP)) (set (match_dup 0) (and:SI (match_dup 0) (const_int 1)))] "")
It's actually the MSB that is affected, and the entire register is set to zero if a == b. Basically cmp/cmpu prepare rD so that a signed compare-with-zero-and-branch will do the requested conditional branch.
So, branches are easy, but cstores are tricky. Something like this should work; indeed you do not need any CC mode:
There are some other quirks with the MicroBlaze architecture. The cmp/cmpu instructions only take a register. Other instructions which can be used for equality or signed comparisons (xor or sub) can take an immediate operand. I'll see how they can be added.
-- Michael Eager eager@eagercon.com 1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
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