Re: generate RTL sequence

[Joern Rennecke <amylaar at spamcop dot net>]

Quoting daniel tian <daniel.xntian@gmail.com>:

> Hi,
>     I have a problem about RTL sequence.
>     If I wanna generate the RTL in sequence, and don't let gcc to   
> schedule them.
>     Like the following(all the variable is rtx):
>
>     emit_insn(reg0,  operands[0]);
>     emit_insn(reg1,  reg0);
>     emit_insn(operands[0],  reg1);
>
>     But gcc will will reorder the three rtl in optimization.
>     I just wanna the those rtl in one block as a unit, don't let the
> gcc disrupt the sequence.
>     How can I do it?

If you want to merely fix the order of the instructions relative to
each other, you can do this by adding an explicit dependency in the
rtl.  I.e. you can invent some hard register (or model an actual one
if there is one that is the reason for your ordering requirements),
set it in the first instruction, use and set it in the second insn,
and use it in the third insn.  You can use UNSPEC and dependencies
on other inputs to avoid some undesired compiler transformation like
from combine.

If you need more rigid scheduling, you can use CC0.