;; Function main (main) ## max_blk: 0 ## max_regno: 43 ## max_allocno: 2 ## Compressed triangular bitmatrix size: 1 bits, 1 bytes ## Standard triangular bitmatrix size: 1 bits, 1 bytes [100.00%] ## Square bitmatrix size: 4 bits, 1 bytes [100.00%] 31 REG_N_REFS=0, REG_FREQ=0, REG_LIVE_LENGTH=0 32 REG_N_REFS=0, REG_FREQ=0, REG_LIVE_LENGTH=0 33 REG_N_REFS=0, REG_FREQ=0, REG_LIVE_LENGTH=0 34 REG_N_REFS=0, REG_FREQ=0, REG_LIVE_LENGTH=0 35 REG_N_REFS=0, REG_FREQ=0, REG_LIVE_LENGTH=0 36 REG_N_REFS=0, REG_FREQ=0, REG_LIVE_LENGTH=0 37 REG_N_REFS=4, REG_FREQ=4000, REG_LIVE_LENGTH=6 38 REG_N_REFS=0, REG_FREQ=0, REG_LIVE_LENGTH=0 39 REG_N_REFS=0, REG_FREQ=0, REG_LIVE_LENGTH=0 40 REG_N_REFS=0, REG_FREQ=0, REG_LIVE_LENGTH=0 41 REG_N_REFS=0, REG_FREQ=0, REG_LIVE_LENGTH=0 42 REG_N_REFS=2, REG_FREQ=2000, REG_LIVE_LENGTH=8 regs_ever_live = 2 15 17 fixed registers : 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 starting basic block 2 insn = 8 live = hardregs [] renumbered [] pseudos [ 37 42] adding def 42 roc adding 42<=>(37 42 ) clearing def 42 insn = 6 live = hardregs [] renumbered [] pseudos [ 37] adding def 37 roc adding 37<=>(37 ) clearing def 37 starting basic block 3 insn = 13 live = hardregs [] renumbered [] pseudos [ 37 42] seeing use 37 insn = 9 live = hardregs [] renumbered [] pseudos [ 37 42] adding def 17 clearing def 0 clearing def 1 clearing def 2 clearing def 3 clearing def 4 clearing def 5 clearing def 6 clearing def 7 clearing def 8 clearing def 9 clearing def 10 clearing def 11 clearing def 12 clearing def 13 clearing def 16 clearing def 17 clearing def 18 clearing def 19 clearing def 20 clearing def 21 clearing def 22 clearing def 23 clearing def 24 clearing def 25 clearing def 26 clearing def 27 clearing def 28 clearing def 29 seeing use 15 seeing use 42 insn = 10 live = hardregs [] renumbered [] pseudos [ 37 42] adding def 37 roc adding 37<=>(37 ) clearing def 37 seeing use 37 dying pseudo starting early clobber conflicts. starting basic block 4 insn = 25 live = hardregs [2 ] renumbered [] pseudos [] seeing use 2 insn = 19 live = hardregs [2 ] renumbered [] pseudos [] adding def 2 clearing def 2 ;; 2 regs to allocate: 37 42 ;; 37 conflicts: 42 ;; 42 conflicts: 37 insn=6, live_throughout: 15, dead_or_set: insn=8, live_throughout: 15, dead_or_set: insn=11, live_throughout: 15, dead_or_set: insn=10, live_throughout: 15, dead_or_set: insn=9, live_throughout: 15, dead_or_set: insn=13, live_throughout: 15, dead_or_set: insn=19, live_throughout: 15, dead_or_set: 2 insn=25, live_throughout: 2, 15, dead_or_set: init_insns for 42: (insn_list:REG_DEP_TRUE 8 (nil)) Spilling for insn 6. Using reg 4 for reload 0 Spilling for insn 10. Using reg 4 for reload 1 Spilling for insn 9. Using reg 0 for reload 0 Spilling for insn 13. Using reg 4 for reload 0 Spilling for insn 6. Using reg 4 for reload 0 Spilling for insn 10. Using reg 4 for reload 1 Spilling for insn 9. Using reg 0 for reload 0 Spilling for insn 13. Using reg 4 for reload 0 deleting insn with uid = 8. Reloads for insn # 6 Reload 0: reload_out (SI) = (reg/v:SI 37 [ i ]) GENERAL_REGS, RELOAD_FOR_OUTPUT (opnum = 0) reload_out_reg: (reg/v:SI 37 [ i ]) reload_reg_rtx: (reg:SI 0 R0) Reloads for insn # 10 Reload 0: GENERAL_REGS, RELOAD_FOR_OUTPUT (opnum = 0) reload_out_reg: (reg/v:SI 37 [ i ]) Reload 1: reload_in (SI) = (reg/v:SI 37 [ i ]) reload_out (SI) = (reg/v:SI 37 [ i ]) GENERAL_REGS, RELOAD_OTHER (opnum = 1) reload_in_reg: (reg/v:SI 37 [ i ]) reload_out_reg: (reg/v:SI 37 [ i ]) reload_reg_rtx: (reg:SI 4 R4) Reloads for insn # 9 Reload 0: reload_in (SI) = (symbol_ref:SI ("fun") [flags 0x41] ) R0_REG, RELOAD_FOR_OPERAND_ADDRESS (opnum = 0), can't combine reload_in_reg: (reg/f:SI 42) reload_reg_rtx: (reg:SI 0 R0) Reloads for insn # 13 Reload 0: reload_in (SI) = (reg/v:SI 37 [ i ]) GENERAL_REGS, RELOAD_FOR_INPUT (opnum = 1) reload_in_reg: (reg/v:SI 37 [ i ]) reload_reg_rtx: (reg:SI 4 R4) ;; Register dispositions: ;; Hard regs used: 0 2 4 15 17 starting the processing of deferred insns ending the processing of deferred insns rescanning insn with uid = 9. deleting insn with uid = 9. starting the processing of deferred insns ending the processing of deferred insns df_analyze called df_worklist_dataflow_overeager:n_basic_blocks 5 n_edges 5 count 5 ( 1) df_worklist_dataflow_overeager:n_basic_blocks 5 n_edges 5 count 6 ( 1.2) main Dataflow summary: ;; invalidated by call 0 [R0] 1 [R1] 2 [R2] 3 [R3] 4 [R4] 5 [R5] 6 [R6] 7 [R7] 8 [R8] 9 [R9] 10 [R10] 11 [R11] 12 [R12] 13 [R13] 16 [PC] 17 [LINK] 18 [LINK_S] 19 [STACK] 20 [STACK_S] 21 [LOOP] 22 [LOOP_S] 23 [STATUS] 24 [STATUS_S] 25 [GBR] 26 [GBRCNT] 27 [AMR] 28 [SPARE] 29 [DEBUG] ;; hardware regs used 15 [R15] ;; regular block artificial uses 15 [R15] ;; eh block artificial uses 15 [R15] 30 [AP] ;; entry block defs 2 [R2] 4 [R4] 5 [R5] 6 [R6] 7 [R7] 15 [R15] ;; exit block uses 2 [R2] 15 [R15] 17 [LINK] ;; regs ever live 0[R0] 2[R2] 4[R4] 15[R15] 17[LINK] (note:HI 2 0 4 NOTE_INSN_DELETED) ;; Start of basic block ( 0) -> 2 ;; bb 2 artificial_defs: { } ;; bb 2 artificial_uses: { u-1(15){ }} ;; lr in 15 [R15] ;; lr use 15 [R15] ;; lr def 0 [R0] ;; live in 15 [R15] ;; live gen 0 [R0] ;; live kill ;; Pred edge ENTRY [100.0%] (fallthru) (note:HI 4 2 3 2 [bb 2] NOTE_INSN_BASIC_BLOCK) (note:HI 3 4 6 2 NOTE_INSN_FUNCTION_BEG) (insn:HI 6 3 37 2 movebug.c:8 (set (reg:SI 0 R0) (const_int 0 [0x0])) 2 {constant_load_si} (expr_list:REG_EQUAL (const_int 0 [0x0]) (nil))) (insn 37 6 8 2 movebug.c:8 (set (mem/c:SI (reg/f:SI 15 R15) [2 i+0 S4 A32]) (reg:SI 0 R0)) 8 {store_si} (nil)) (note:HI 8 37 11 2 NOTE_INSN_DELETED) ;; End of basic block 2 -> ( 3) ;; lr out 0 [R0] 15 [R15] ;; live out 0 [R0] 15 [R15] ;; Succ edge 3 [100.0%] (fallthru) ;; Start of basic block ( 3 2) -> 3 ;; bb 3 artificial_defs: { } ;; bb 3 artificial_uses: { u-1(15){ }} ;; lr in 0 [R0] 15 [R15] ;; lr use 0 [R0] 15 [R15] ;; lr def 0 [R0] 1 [R1] 2 [R2] 3 [R3] 4 [R4] 5 [R5] 6 [R6] 7 [R7] 8 [R8] 9 [R9] 10 [R10] 11 [R11] 12 [R12] 13 [R13] 16 [PC] 17 [LINK] 18 [LINK_S] 19 [STACK] 20 [STACK_S] 21 [LOOP] 22 [LOOP_S] 23 [STATUS] 24 [STATUS_S] 25 [GBR] 26 [GBRCNT] 27 [AMR] 28 [SPARE] 29 [DEBUG] ;; live in 0 [R0] 15 [R15] ;; live gen 4 [R4] ;; live kill 17 [LINK] ;; Pred edge 3 [93.8%] (dfs_back) ;; Pred edge 2 [100.0%] (fallthru) (code_label:HI 11 8 7 3 2 "" [1 uses]) (note:HI 7 11 38 3 [bb 3] NOTE_INSN_BASIC_BLOCK) (insn 38 7 10 3 movebug.c:10 (set (reg:SI 4 R4) (mem/c:SI (reg/f:SI 15 R15) [2 i+0 S4 A32])) 11 {load_si} (nil)) (insn:HI 10 38 39 3 movebug.c:10 (set (reg:SI 4 R4) (plus:SI (reg:SI 4 R4) (const_int 1 [0x1]))) 45 {rice_addsi3} (nil)) (insn 39 10 9 3 movebug.c:10 (set (mem/c:SI (reg/f:SI 15 R15) [2 i+0 S4 A32]) (reg:SI 4 R4)) 8 {store_si} (nil)) (call_insn:HI 9 39 40 3 movebug.c:12 (parallel [ (call (mem:SI (reg:SI 0 R0) [0 S4 A32]) (const_int 0 [0x0])) (clobber (reg:SI 17 LINK)) ]) 99 {call} (nil) (nil)) (insn 40 9 13 3 movebug.c:10 (set (reg:SI 4 R4) (mem/c:SI (reg/f:SI 15 R15) [2 i+0 S4 A32])) 11 {load_si} (nil)) (jump_insn:HI 13 40 14 3 movebug.c:10 (set (pc) (if_then_else (ne:SI (reg:SI 4 R4) (const_int 16 [0x10])) (label_ref:SI 11) (pc))) 84 {*insn_bne} (expr_list:REG_BR_PROB (const_int 9375 [0x249f]) (nil))) ;; End of basic block 3 -> ( 3 4) ;; lr out 0 [R0] 15 [R15] 17 [LINK] ;; live out 0 [R0] 15 [R15] ;; Succ edge 3 [93.8%] (dfs_back) ;; Succ edge 4 [6.2%] (fallthru,loop_exit) ;; Start of basic block ( 3) -> 4 ;; bb 4 artificial_defs: { } ;; bb 4 artificial_uses: { u-1(15){ }} ;; lr in 15 [R15] 17 [LINK] ;; lr use 15 [R15] ;; lr def 2 [R2] ;; live in 15 [R15] ;; live gen 2 [R2] ;; live kill ;; Pred edge 3 [6.2%] (fallthru,loop_exit) (note:HI 14 13 19 4 [bb 4] NOTE_INSN_BASIC_BLOCK) (insn:HI 19 14 25 4 movebug.c:15 (set (reg/i:SI 2 R2 [ ]) (const_int 0 [0x0])) 2 {constant_load_si} (expr_list:REG_EQUAL (const_int 0 [0x0]) (nil))) (insn 25 19 35 4 movebug.c:15 (use (reg/i:SI 2 R2 [ ])) -1 (nil)) ;; End of basic block 4 -> ( 1) ;; lr out 2 [R2] 15 [R15] 17 [LINK] ;; live out 2 [R2] 15 [R15] ;; Succ edge EXIT [100.0%] (fallthru) (note 35 25 36 NOTE_INSN_DELETED) (note 36 35 0 NOTE_INSN_DELETED)