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Re: TLS support on ARM
- From: Daniel Jacobowitz <drow at false dot org>
- To: Thomas Klein <th dot r dot klein at web dot de>
- Cc: gcc at gcc dot gnu dot org
- Date: Thu, 3 Dec 2009 11:13:32 -0500
- Subject: Re: TLS support on ARM
- References: <4B17F0D2.9010701@web.de>
On Thu, Dec 03, 2009 at 05:09:38PM +0000, Thomas Klein wrote:
> This might be the initial plan.
> But is this true?
It is true because a typical implementation of this function has no
need to clobber registers. For instance, glibc's calls a kernel
helper this way:
0x00015810 <__aeabi_read_tp+0>: mvn r0, #61440 ; 0xf000
0x00015814 <__aeabi_read_tp+4>: sub pc, r0, #31
The kernel helper reads from a fixed location or a hardware register,
both of which are a single instruction. No temporary registers are
required.
> A "bl __aeabi_read_tp" call does not exchanging the mode.
> So the program simply crashes.
The linker is responsibe for converting bl to blx, or for inserting
mode changing stubs. It is also responsible for long calls. Unless
you're using a really old linker, I can't see why you would have any
problems. Do you have a concrete problem?
> Is the implementation still incomplete?
No. It's been finished for two years or more.
--
Daniel Jacobowitz
CodeSourcery