For accessing a->b GCC generates the following code:
move.l (sp-16), d3
lsrr.l #<16, d3
move.l (sp-12),d2
asll #<16,d2
or d3,d2
cmpeq.w #<2,d2
jf _L2
Because data registers are 40 bit for 'asll' operation the shift count
should be 16+8 or there should be sign extension from 32bit to 40 bits
after the 'or' operation. The target has instruction to sign extend
from 32bit to 40 bit.
Similarly there are other operation that requires sign/zero extension.
So is there any way to tell GCC that the data registers are 40bit and
there by expect it to generate sign/zero extension accordingly ?