Re: Register Pressure in Instruction Level Parallelism

[Michael Kruse <meinert at uni-paderborn dot de>]

Hi,

Albert Cohen schrieb:
> Unfortunately, the state of the art (more recent that the thesis 
> referenced in the original email, see Touati's web page) is limited to 
> basic block and software-pipelining scopes, and limited to scheduling.
Do have any specific publication in mind? At the moment, my concerns are 
basic blocks only. As far as I can see from the web page, you are 
working on an implementation called DDG. I could not find a download 
link (except for some headers and examples).

> However, I will strongly advise anybody (= Kenny Zadeck) looking at a 
> fresh SSA-based backend design to consider such an approach to avoid 
> messing up with pressure-aware-* where * is any backend pass that 
> bears a risk of blowing up register pressure.
I don't know the deep internals of the gcc yet, but I think it is 
doable. My main work is to evaluate the effectiveness of this technique. 
I don't know of any later passes which introduce new register 
requirements. And even if... the mighty reload pass must be able to 
handle this. I am interested in a comparison to what there has been before.

> If you interested in collaboration on the topic, we are about to start 
> extending those approaches to general control-flow, and implementing 
> it in a production compiler (not GCC, but a free one, and not LLVM 
> either).
At the moment, I am most interested in writing a thesis. And since this 
is the topic, this means that I am interested, yes. Especially how you 
generalized it.

It might also be interesting for my advisor and the professor. 
Otherwise, we might end up in doing redundant work.

Btw, if it is a free compiler, why not telling us which one?

Regards,
Michael Kruse

--
Tardyzentrismus verboten!

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