Re: scheduling question

[Vladimir Makarov <vmakarov at redhat dot com>]

Alex Turjan wrote:
> --- On Thu, 5/7/09, Maxim Kuvyrkov <maxim@codesourcery.com> wrote:
>
> > From: Maxim Kuvyrkov <maxim@codesourcery.com>
> > Subject: Re: scheduling question
> > To: aturjan@yahoo.com
> > Cc: "Vladimir Makarov" <vmakarov@redhat.com>, gcc@gcc.gnu.org
> > Date: Thursday, May 7, 2009, 1:01 PM
> > Alex Turjan wrote:
> > > Hi,
> > > During scheduling Im confronted with the fact that an
> > instruction is moved
> > > from the ready list to queued with the cost 2, while
> > according to my
> > > expectations the insn should have been moved to queued
> > with cost 1.
> > > Did anybody experience similar problem? 
> > From what you described it's not clear what the problem
> > is.  When scheduler infers that an instruction cannot be
> > scheduled in the next N cycles (due to DFA hazard or
> > insn_cost/dep_cost hook considerations or due to something
> > else) the scheduler queues the instruction on (N+1) cycle.
>
> The point is that in found a case in which an insn is moved to queued with cost 2 while it could have been issued in next cycle (which corresponds to queued with cost 1). 
>
> I think the problem is not in the automaton state transition but in the vector_min_issue_delay. Do you have some documentation of the way vector_min_issue_delay is constructed?
It is pretty simple recursive algorithm.  Please, see function 
genautomata.c::min_issue_delay_pass_states.

In brief we have a graph which nodes are states and arcs are marked by 
insns which means transition from one state to another one when the insn 
is issued.  Some arcs are marked by "cycle advance" it means changing 
state when a new processor clock starts.  So staring with a given state 
we are searching a state, where there is an outgoing arc marked by given 
insn, connected by a path with minimal numbers of "cycle advance" arcs 
on the path.  The # of such "cycle advance" arcs is the value of 
vector_min_issue_delay for given state and insn.
>