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Re: Reserving a number of consecutive registers

From: Alexandre Pereira Nunes <alexandre dot nunes at gmail dot com>
To: gcc at gcc dot gnu dot org
Date: Mon, 20 Apr 2009 13:59:37 -0300
Subject: Re: Reserving a number of consecutive registers
References: <c568a2600904171150y27a14be3x380a7fa2e967280e@mail.gmail.com> <c568a2600904200646x4f6ac355k165d6a4925b2aacc@mail.gmail.com> <200904201836.44013.ebotcazou@adacore.com> <c568a2600904200933j54326d94u8881a22465009c7f@mail.gmail.com> <3b6faf240904200957x7e5c5662n9c05f312fedccb57@mail.gmail.com>

On Mon, Apr 20, 2009 at 1:33 PM, fearyourself <fearyourself@gmail.com> wrote:
>
> For the moment, we will be remaining in the 4.3.2 version and have no
> plans to follow the next 4.4/4.5 versions.
>
> Does any architecture do such a "machine-specific reorg" pass. I've
> looked around and haven't really seen one. Could you give me an idea
> of where to look and how exactly that would work?
>
> Thanks a lot,
> Jc

ARM has multiple load/store and it had some predictable support in gcc
4.3.x, perhaps you can take a look at it. But it was far from good,
IMHO, see PR9831 for details.

References:
- Reserving a number of consecutive registers
  - From: fearyourself
- Re: Reserving a number of consecutive registers
  - From: fearyourself
- Re: Reserving a number of consecutive registers
  - From: Eric Botcazou
- Re: Reserving a number of consecutive registers
  - From: fearyourself

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