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Re: help for arm avr bfin cris frv h8300 m68k mcore mmix pdp11 rs6000 sh vax
- From: Alexandre Oliva <aoliva at redhat dot com>
- To: Paolo Bonzini <bonzini at gnu dot org>
- Cc: "gcc\ at gcc dot gnu dot org" <gcc at gcc dot gnu dot org>, richard dot earnshaw at arm dot com, bernd dot schmidt at analog dot com, hp at axis dot com, aldyh at redhat dot com, law at redhat dot com, nickc at redhat dot com, kazu at codesourcery dot com, ni1d at arrl dot net, kkojima at gcc dot gnu dot org, matt at 3am-software dot com
- Date: Tue, 31 Mar 2009 20:37:15 -0300
- Subject: Re: help for arm avr bfin cris frv h8300 m68k mcore mmix pdp11 rs6000 sh vax
- References: <f865508f0903130434i795ab1ck7c6d4e840951279@mail.gmail.com>
On Mar 13, 2009, Paolo Bonzini <bonzini@gnu.org> wrote:
> For 4.5 I would like to improve our RTL canonicalization so that no
> out-of-range shifts are ever in the RTL representation.
FR-V non-vector shifts truncate a register shift count to 5 bits; it's
from the ISA specs, it doesn't appear that the same truncation is
applied to 10- or 12-bit immediate shift operands. Vector shifts
truncate the 6-bit immediate shift count to 4 bits.
--
Alexandre Oliva, freedom fighter http://FSFLA.org/~lxoliva/
You must be the change you wish to see in the world. -- Gandhi
Be Free! -- http://FSFLA.org/ FSF Latin America board member
Free Software Evangelist Red Hat Brazil Compiler Engineer