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Re: Is there any plan for "data propagation from Tree SSA to RTL" to be in GCC mainline?
- From: "Steven Bosscher" <stevenb dot gcc at gmail dot com>
- To: "Bingfeng Mei" <bmei at broadcom dot com>
- Cc: "gcc at gcc dot gnu dot org" <gcc at gcc dot gnu dot org>, "dm at ispras dot ru" <dm at ispras dot ru>, "Daniel Berlin" <dberlin at dberlin dot org>
- Date: Sun, 9 Nov 2008 12:38:37 +0100
- Subject: Re: Is there any plan for "data propagation from Tree SSA to RTL" to be in GCC mainline?
- References: <7FB04A5C213E9943A72EE127DB74F0AD24F3C30240@SJEXCHCCR02.corp.ad.broadcom.com>
On Mon, Nov 3, 2008 at 5:00 PM, Bingfeng Mei <bmei@broadcom.com> wrote:
> Hello,
> I found current modulo pipelining very inefficient for many loops. One reason is primitive cross-iteration memory dependency analysis. The add_inter_loop_mem_dep function in ddg.c just draws true dependency between every write and read pair. This is quite inadequate since many loops read from memory at the beginning of the loop and wrte to the memory at the end. In the end, we obtain schedule no better than list scheduling.
>
>
> I am aware of this work of propagating Tree-level dependency info to RTL (http://sysrun.haifa.il.ibm.com/hrl/greps2007/papers/melnik-propagation-greps2007.pdf). It should help a lot in improving memory dependency analysis. Is there any plan for this work to make into GCC mainline? Thanks in advance.
Wasn't there a GSoC project for this last year? And this year?
It'd be interesting to hear if anything came out of that...
Gr.
Steven