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Pipeline hazards and delay slots
- From: "Mohamed Shafi" <shafitvm at gmail dot com>
- To: gcc at gcc dot gnu dot org
- Date: Sat, 3 May 2008 17:16:23 +0530
- Subject: Pipeline hazards and delay slots
Hello all,
In the gcc port that i am currently working on delay slots are getting
filled with instructions that require a nop between them.
Say,
call fun
lw R0, R8
add R1, R0
This is an example where both the delay slots have been filled.
But 'add' instruction has a true data dependency on 'lw' instructions
and require a delay of one cycle between them. Noramlly this is done
by inserting a nop between such instructions if instruction scheduler
doesn't schedule instructions properly. Currently i am doing this in
final_prescan just like in MorphoRISC1 (mt).
But how can i handle instances like this? Should i be doing insertion
of nops in reorg pass?
Thanks for your time.
Regards,
Shafi