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Committed: fix cris.md strict_low_part constraints (was: Re: A doubt about constraint modifiers)
- From: Hans-Peter Nilsson <hans-peter dot nilsson at axis dot com>
- To: bernds_cb1 at t-online dot de
- Cc: shafitvm at gmail dot com, gcc at gcc dot gnu dot org, gcc-patches at gcc dot gnu dot org
- Date: Sun, 13 Apr 2008 02:53:26 +0200
- Subject: Committed: fix cris.md strict_low_part constraints (was: Re: A doubt about constraint modifiers)
> Date: Fri, 11 Apr 2008 15:32:02 +0200
> From: Bernd Schmidt <bernds_cb1@t-online.de>
> Mohamed Shafi wrote:
> > In cris i saw this patten
> >
> > (define_insn "*andhi_lowpart"
> > [(set (strict_low_part
> > (match_operand:HI 0 "register_operand" "=r,r, r,r,r,r"))
> > (and:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r")
> > (match_operand:HI 2 "general_operand" "r,Q>,L,O,g,!To")))]
> >
> > Here = is used.
>
> This is incorrect since when the last alternative matches, nothing tells
> the compiler that operand 0 is also an input.
Oops, thanks for noticing. For consistency, I made all
strict_low_part constraints use "+", including those where all
alternatives had %0. Regtested cross to cris-elf and
crisv32-elf.
PS. I'm not a native speaker, but FWIW I agree with Joe Buck
regarding usage of the word "doubt", but I see it's quite common
with some non-native speakers, indicating the fault is at the
teaching level.
gcc:
* config/cris/cris.md ("*andhi_lowpart_non_v32", "*andhi_lowpart_v32")
("*andqi_lowpart_non_v32", "*andqi_lowpart_v32"): Use "+" for the
operand 0 constraint, not "=".
Index: config/cris/cris.md
===================================================================
--- config/cris/cris.md (revision 134224)
+++ config/cris/cris.md (working copy)
@@ -2958,7 +2958,7 @@ (define_insn "*expanded_andhi_v32"
(define_insn "*andhi_lowpart_non_v32"
[(set (strict_low_part
- (match_operand:HI 0 "register_operand" "=r,r, r,r,r,r"))
+ (match_operand:HI 0 "register_operand" "+r,r, r,r,r,r"))
(and:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r")
(match_operand:HI 2 "general_operand" "r,Q>,L,O,g,!To")))]
"!TARGET_V32"
@@ -2974,7 +2974,7 @@ (define_insn "*andhi_lowpart_non_v32"
(define_insn "*andhi_lowpart_v32"
[(set (strict_low_part
- (match_operand:HI 0 "register_operand" "=r,r,r,r,r"))
+ (match_operand:HI 0 "register_operand" "+r,r,r,r,r"))
(and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
(match_operand:HI 2 "general_operand" "r,Q>,L,O,g")))]
"TARGET_V32"
@@ -3025,7 +3025,7 @@ (define_insn "*andqi3_v32"
(define_insn "*andqi_lowpart_non_v32"
[(set (strict_low_part
- (match_operand:QI 0 "register_operand" "=r,r, r,r,r"))
+ (match_operand:QI 0 "register_operand" "+r,r, r,r,r"))
(and:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0,r")
(match_operand:QI 2 "general_operand" "r,Q>,O,g,!To")))]
"!TARGET_V32"
@@ -3040,7 +3040,7 @@ (define_insn "*andqi_lowpart_non_v32"
(define_insn "*andqi_lowpart_v32"
[(set (strict_low_part
- (match_operand:QI 0 "register_operand" "=r,r,r,r"))
+ (match_operand:QI 0 "register_operand" "+r,r,r,r"))
(and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0")
(match_operand:QI 2 "general_operand" "r,Q>,O,g")))]
"TARGET_V32"
brgds, H-P