This is the mail archive of the gcc@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [trunk] Addition to subreg section of rtl.text.


Bernd Schmidt wrote:
Joern Rennecke wrote:
And @code{(subreg:SI (reg:DF 10) 0)} would be a natural way to express that
you are using the floating point register as a 32 bit integer register,
with writes clobbering the entire 64 bit of the register.
Yes, this is one possible definition. But there's no reason in this
situation why you couldn't just use a single REG. Why use subregs at all?

Because before reload, you use pseudos. And in order for
(subreg:SI (reg:DF ...) ...) to be viable, it still has to be viable between
hard register allocation and alter_reg.

Is that even valid? Are there any known ports using this? AFAIR the middle-end doesn't create this (although it will use (subreg:SF (reg:DI)).

SPE has patterns for


[(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
      (subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 4))]

for example.

Paolo


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]