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Re: Test Harness and SPARC VIS Instructions
- From: "Seongbae Park (박성배, 朴成培)" <seongbae dot park at gmail dot com>
- To: "Joel Sherrill" <joel dot sherrill at oarcorp dot com>
- Cc: "Uros Bizjak" <ubizjak at gmail dot com>, GCC <gcc at gcc dot gnu dot org>
- Date: Thu, 13 Mar 2008 13:06:24 -0700
- Subject: Re: Test Harness and SPARC VIS Instructions
- References: <47D979DB.email@example.com> <47D98149.firstname.lastname@example.org>
On Thu, Mar 13, 2008 at 12:32 PM, Joel Sherrill
> Uros Bizjak wrote:
> > Hello!
> >> Can someone familiar with VIS provide an instruction
> >> that is OK to do a run-time test with to check if
> >> it is supported?
> > Perhaps this fragment from testsuite/gcc.dg/vect/tree-vect.h may help:
> > #elif defined(__sparc__)
> > asm volatile (".word\t0x81b007c0");
> Thanks. That helped a lot. Now I only see these cases on vect.exp
> This one looks like another test slipping another unsupported
> instruction by.
> 0x020012b8 <fbar+40>: bne,pn %icc, 0x200138c <fbar+252>
> Is this UltraSPARC and not V7? Do we need two bad instructions
> in the test case?
Branc with prediction is v9. Even v8 doesn't have it. No v8 processor has VIS,
so actually this test is sufficient. If you really want v7 check (not v8 check),
then you should use something else like, umul,
which is only available on v8 and up.