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On Fri, Feb 1, 2008 at 3:55 PM, Andrew MacLeod <amacleod@redhat.com> wrote:
1 - Pass cleanup. There have been rumblings about this, but I haven't
Yes, this is an area that is in desperate need of TLC. Your plan looks good to me. We need to have a mechanism to determine whether a pass did something, we need to be able to have different pipelines for different architectures.
Do you have anything specific in mind? Create a branch? Work
directly on mainline?
Richi's work will probably change what the web looks like, so this seems like a good item for me to defer for a bit until we see where we end up.2 - Interface to the virtual operands. The virtual operand web provides what really amounts to low level detail of memory accesses. Every pass
Agreed. SRA needs a new implementation.3 - SRA. There appear to be some deficiencies in SRA, and also how it interacts with the MEMSSA partitioner. I found when looking at some 4.3
4 - SSA pressure reduction. I'm throwing this back on the table. I never
quite got around to it before, and nothing has changed to resolve the
issues. We freely create as much register pressure in the SSA optimizers
as we want (as we should be able to). The backend has doing nothing to
address the issue and the RTL register allocator is simply swamped by
the sheer quantity of live ranges sometimes. Perhaps Vlad's RA will get
in this release, and/or perhaps the need for this will be eliminated by
something else, but it is something that may help code generation in the
short term at least.
What about the RTL expansion from SSA directly? This is an area that is going to affect the tuples branch very soon. We are currently going into RTL from tuples directly (no TER), but since most passes have not been converted, I can yet tell how much of a problem this is. In a few weeks we'll hit this problem.
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