Re: volatile and R/M/W operations

[kenner at vlsi1 dot ultra dot nyu dot edu (Richard Kenner)]

> OK, sounds reasonable, but then I don't understand the logic behind
> avoiding this instruction sequence for the volatile case, this is
> two accesses at the bus level so what's the difference? 

There's no difference from that perspective.  The logic behind what's
generated is that instead of trying to do a case-by-case analysis of
what instruction combinations might actually be valid for volatile
memory (which could potentially be target-specific), GCC takes the
conservative approach of simply disabling all but trivial combinations
for volatile access.