Re: [RFC][modulo-sched] Fix scheduling order within a cycle

[Revital1 Eres <ERES at il dot ibm dot com>]

Hello,

Following our off-line discussion; attached is the dump file of the
problematic testcase. (sms-4.c)

Here are some relevant details:

insn 61(write) and 58(read) were swapped, so sms tries to generate some
kind of reg-move and fails.

[CYCLE 4 ]: 61, 58,

insn 61 is the only already scheduled instruction which insn 58 depends
on.

The window of insn 58 is (4 .. -1), calculated as follows:

Processing edge: [61 -(T,14,1)-> 58]
Scheduling 8 (58) in psp_pss_not_empty, checking p 11 (61): pred st = 4;
early_start = 0; latency: 14
Processing edge: [58 -(A,0,0)-> 61]
Scheduling 8 (58) in psp_pss_not_empty, checking s 11 (61): succ st = 4;
late_start = 4; latency: 0
Processing edge: [58 -(T,2,0)-> 59]
Scheduling 8 (58) in psp_pss_not_empty, checking s 9 (59): the node is not
scheduled

Trying to schedule node 8                         INSN = 58  in (4 .. -1)
step -1
Scheduled w/o split in 4

insn 61 only must_preceed insn 58 because the latency between 61->58 is
14 which causes the end boundary of the window to be 0.

Thanks,
Revital

(See attached file: test.c.172r.sms)

Attachment: test.c.172r.sms
Description: Binary data