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Re: Scheduling problem - A more detailed explain
So, my question becomes clear:
How to solve this problem by making GCC knows the data dependencies
between mov X = pr (or mov pr = X, -1) and other usage of a specific
predicate register (e.g. p6, p7)?
We already have support for these move instructions. See the
movdi_internal pattern. Since there are 64 1-bit PR registers, we use a
DImode reference to pr0 to represent the entire set of PR registers. Is
this the RTL that you are using? Or do you have your own
representation? If different, what RTL are you using?
Personally speaking, I think I need to modify itanium1.md or
itanium2.md to instruct GCC to notice these dependencies (However,
these files look too much complex :-(); or is there any simpler way to
get around this problem ?
You don't need to touch the itanium1.md or itanium2.md files for this
issue. They are only for pipeline info. Dependency info is handled in
rtx_needs_barrier and friends in ia64.c.
rws_access_reg should be handling this correctly. It uses
HARD_REGNO_NREGS to get the number of regs referred to by a reg rtl. So
it should return 64 in this case, and then it will iterate over all
64-bit PR regs when checking for a dependency.
So this should work if you are using the correct RTL representation. If
you are using a different RTL representation, it won't work.
Jim Wilson, GNU Tools Support, http://www.specifix.com