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REG_ALLOC_ORDER and Altivec registers
- From: Revital1 Eres <ERES at il dot ibm dot com>
- To: gcc at gcc dot gnu dot org
- Date: Thu, 1 Mar 2007 10:37:36 +0200
- Subject: REG_ALLOC_ORDER and Altivec registers
Hello,
I wonder why this order (non-consecutive, decreasing) of Altivec registers
was chosen when specifying the allocation order in REG_ALLOC_ORDER.
(taken from rs6000.h)
/* AltiVec registers. */ \
77, 78, \
90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
79, \
96, 95, 94, 93, 92, 91, \
108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
109, 110, \
111, 112, 113 \
Thanks,
Revital