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Re: Abt long long support
On 11/7/06, Mike Stump <mrs@apple.com> wrote:
On Nov 6, 2006, at 9:30 PM, Mohamed Shafi wrote:
> My target (non gcc/private one) fails for long long testcases
Does it work flawlessly otherwise, if not, fix all those problems
first. After those are all fixed, then you can see if it then just
works. In particular, you will want to ensure that 32 bit things
work fine, first.
Well, the test cases fails only for one condition.
when main calls a function, like llabs ,to find the absolute value of
a negative number and the function performs the action with
return (arg<0 ? -arg : arg );
The program works fine if i pass a
1.positive value
2.use -fomit-frame-pointer flag while compiling (with negative value)
3.use another variable in function body to return i.e
long long foo(long long x){
long long k;
k=(x<0 ? -x : x);
return k;
}
When i diff the rtl dumps for programs passing negative value with and
without frame pointer i find changes from file.greg . Thats when the
frame pointer issue kicks in.
This is a small test case which produces the bug
#include<stdio.h>
long long fun(long long k)
{
return ( k>0 ? k : -k);
}
int main()
{
long long i= -1;
if(fun(i) == 1)
printf("\nsuccess \n");
else
printf("\nfailure \n");
}
here the relevant rtl dump for the function fun from .greg file
; Hard regs used: 0 1 2 3 12 13 14 21
(note 2 0 9 NOTE_INSN_DELETED)
;; Start of basic block 0, registers live: 0 [d0] 1 [d1] 14 [a6] 15
[a7] 22 [vAP]
(note 9 2 4 0 [bb 0] NOTE_INSN_BASIC_BLOCK)
(insn 4 9 5 0 (parallel [
(set (reg/f:SI 13 a5 [31])
(plus:SI (reg/f:SI 14 a6)
(const_int -8 [0xfffffff8])))
(clobber (reg:CC 21 cc))
]) 29 {addsi3} (nil)
(nil))
(insn 5 4 6 0 (set (mem/c/i:SI (reg/f:SI 13 a5 [31]) [0 k+0 S4 A32])
(reg:SI 0 d0 [ k ])) 16 {movsi_store} (nil)
(nil))
(insn 6 5 7 0 (set (mem/c/i:SI (plus:SI (reg/f:SI 13 a5 [31])
(const_int 4 [0x4])) [0 k+4 S4 A32])
(reg:SI 1 d1 [orig:0 k+4 ] [0])) 16 {movsi_store} (nil)
(nil))
(note 7 6 13 0 NOTE_INSN_FUNCTION_BEG)
(insn 13 7 14 0 (parallel [
(set (reg/f:SI 13 a5 [33])
(plus:SI (reg/f:SI 14 a6)
(const_int -8 [0xfffffff8])))
(clobber (reg:CC 21 cc))
]) 29 {addsi3} (nil)
(nil))
(insn 14 13 63 0 (set (reg:SI 0 d0)
(mem/c/i:SI (reg/f:SI 13 a5 [33]) [0 k+0 S4 A32])) 15 {movsi_load} (nil)
(nil))
(insn 63 14 64 0 (set (reg:SI 12 a4)
(const_int -16 [0xfffffff0])) 17 {movsi_short_const} (nil)
(nil))
(insn 64 63 65 0 (parallel [
(set (reg:SI 12 a4)
(plus:SI (reg:SI 12 a4)
(reg/f:SI 14 a6)))
(clobber (reg:CC 21 cc))
]) 29 {addsi3} (nil)
(expr_list:REG_EQUIV (plus:SI (reg/f:SI 14 a6)
(const_int -16 [0xfffffff0]))
(nil)))
(insn 65 64 15 0 (set (mem/c:SI (reg:SI 12 a4) [0 D.1863+0 S8 A32])
(reg:SI 0 d0)) 16 {movsi_store} (nil)
(nil))
(insn 15 65 68 0 (set (reg:SI 0 d0)
(mem/c/i:SI (plus:SI (reg/f:SI 13 a5 [33])
(const_int 4 [0x4])) [0 k+4 S4 A32])) 15 {movsi_load} (nil)
(nil))
(insn 68 15 69 0 (set (reg:SI 12 a4)
(const_int -12 [0xfffffff4])) 17 {movsi_short_const} (nil)
(nil))
(insn 69 68 70 0 (parallel [
(set (reg:SI 12 a4)
(plus:SI (reg:SI 12 a4)
(reg/f:SI 14 a6)))
(clobber (reg:CC 21 cc))
]) 29 {addsi3} (nil)
(expr_list:REG_EQUIV (plus:SI (reg/f:SI 14 a6)
(const_int -12 [0xfffffff4]))
(nil)))
(insn 70 69 73 0 (set (mem/c:SI (reg:SI 12 a4) [0 D.1863+0 S8 A32])
(reg:SI 0 d0)) 16 {movsi_store} (nil)
(nil))
(insn 73 70 74 0 (set (reg:SI 12 a4)
(const_int -16 [0xfffffff0])) 17 {movsi_short_const} (nil)
(nil))
(insn 74 73 75 0 (parallel [
(set (reg:SI 12 a4)
(plus:SI (reg:SI 12 a4)
(reg/f:SI 14 a6)))
(clobber (reg:CC 21 cc))
]) 29 {addsi3} (nil)
(expr_list:REG_EQUIV (plus:SI (reg/f:SI 14 a6)
(const_int -16 [0xfffffff0]))
(nil)))
(insn 75 74 17 0 (set (reg:SI 12 a4)
(mem/c:SI (reg:SI 12 a4) [0 D.1863+0 S8 A32])) 15 {movsi_load} (nil)
(nil))
(insn 17 75 18 0 (set (reg:CC 21 cc)
(compare:CC (reg:SI 12 a4)
(const_int 0 [0x0]))) 67 {*cmpsi_internal0} (nil)
(nil))
(jump_insn 18 17 50 0 (set (pc)
(if_then_else (gt:CC (reg:CC 21 cc)
(const_int 0 [0x0]))
(label_ref 32)
(pc))) 41 {*branch_true} (nil)
(nil))
;; End of basic block 0, registers live:
14 [a6] 15 [a7] 22 [vAP] 28
;; Start of basic block 2, registers live: 14 [a6] 15 [a7] 22 [vAP] 28
(note 50 18 78 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 78 50 79 2 (set (reg:SI 13 a5)
(const_int -16 [0xfffffff0])) 17 {movsi_short_const} (nil)
(nil))
(insn 79 78 80 2 (parallel [
(set (reg:SI 13 a5)
(plus:SI (reg:SI 13 a5)
(reg/f:SI 14 a6)))
(clobber (reg:CC 21 cc))
]) 29 {addsi3} (nil)
(expr_list:REG_EQUIV (plus:SI (reg/f:SI 14 a6)
(const_int -16 [0xfffffff0]))
(nil)))
(insn 80 79 19 2 (set (reg:SI 13 a5)
(mem/c:SI (reg:SI 13 a5) [0 D.1863+0 S8 A32])) 15 {movsi_load} (nil)
(nil))
(insn 19 80 20 2 (set (reg:CC 21 cc)
(compare:CC (reg:SI 13 a5)
(const_int 0 [0x0]))) 67 {*cmpsi_internal0} (nil)
(nil))
(jump_insn 20 19 51 2 (set (pc)
(if_then_else (ne:CC (reg:CC 21 cc)
(const_int 0 [0x0]))
(label_ref 27)
(pc))) 41 {*branch_true} (nil)
(nil))
;; End of basic block 2, registers live:
14 [a6] 15 [a7] 22 [vAP] 28
;; Start of basic block 3, registers live: 14 [a6] 15 [a7] 22 [vAP] 28
(note 51 20 83 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 83 51 84 3 (set (reg:SI 12 a4)
(const_int -12 [0xfffffff4])) 17 {movsi_short_const} (nil)
(nil))
(insn 84 83 85 3 (parallel [
(set (reg:SI 12 a4)
(plus:SI (reg:SI 12 a4)
(reg/f:SI 14 a6)))
(clobber (reg:CC 21 cc))
]) 29 {addsi3} (nil)
(expr_list:REG_EQUIV (plus:SI (reg/f:SI 14 a6)
(const_int -12 [0xfffffff4]))
(nil)))
(insn 85 84 21 3 (set (reg:SI 12 a4)
(mem/c:SI (reg:SI 12 a4) [0 D.1863+0 S8 A32])) 15 {movsi_load} (nil)
(nil))
(insn 21 85 22 3 (set (reg:CC 21 cc)
(compare:CC (reg:SI 12 a4)
(const_int 0 [0x0]))) 67 {*cmpsi_internal0} (nil)
(nil))
(jump_insn 22 21 52 3 (set (pc)
(if_then_else (gtu:CC (reg:CC 21 cc)
(const_int 0 [0x0]))
(label_ref 32)
(pc))) 41 {*branch_true} (nil)
(nil))
;; End of basic block 3, registers live:
14 [a6] 15 [a7] 22 [vAP] 28
;; Start of basic block 4, registers live: 14 [a6] 15 [a7] 22 [vAP] 28
(note 52 22 27 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
;; End of basic block 4, registers live:
14 [a6] 15 [a7] 22 [vAP] 28
;; Start of basic block 6, registers live: 14 [a6] 15 [a7] 22 [vAP] 28
(code_label 27 52 54 6 3 "" [1 uses])
(note 54 27 28 6 [bb 6] NOTE_INSN_BASIC_BLOCK)
(insn 28 54 29 6 (set (reg:SI 0 d0)
(const_int 0 [0x0])) 17 {movsi_short_const} (nil)
(nil))
(insn 29 28 90 6 (set (reg:SI 1 d1 [orig:34+4 ] [34])
(const_int 0 [0x0])) 17 {movsi_short_const} (nil)
(nil))
(insn 90 29 91 6 (set (reg:SI 12 a4)
(const_int -16 [0xfffffff0])) 17 {movsi_short_const} (nil)
(nil))
(insn 91 90 94 6 (parallel [
(set (reg:SI 12 a4)
(plus:SI (reg:SI 12 a4)
(reg/f:SI 14 a6)))
(clobber (reg:CC 21 cc))
]) 29 {addsi3} (nil)
(expr_list:REG_EQUIV (plus:SI (reg/f:SI 14 a6)
(const_int -16 [0xfffffff0]))
(nil)))
(insn 94 91 95 6 (set (reg:SI 12 a4)
(mem/c:SI (reg:SI 12 a4) [0 D.1863+0 S4 A32])) 15 {movsi_load} (nil)
(nil))
(insn 95 94 31 6 (set (reg:SI 13 a5 [orig:12+4 ] [12])
(mem/c:SI (plus:SI (reg:SI 12 a4)
(const_int 4 [0x4])) [0 D.1863+4 S4 A32])) 15 {movsi_load} (nil)
(nil))
(insn 31 95 87 6 (parallel [
(set (reg:DI 2 d2)
(minus:DI (reg:DI 0 d0 [34])
(reg:DI 12 a4)))
(clobber (reg:CC 21 cc))
]) 33 {subdi3} (nil)
(nil))
(insn 87 31 88 6 (set (reg:SI 13 a5)
(const_int -16 [0xfffffff0])) 17 {movsi_short_const} (nil)
(nil))
(insn 88 87 92 6 (parallel [
(set (reg:SI 13 a5)
(plus:SI (reg:SI 13 a5)
(reg/f:SI 14 a6)))
(clobber (reg:CC 21 cc))
]) 29 {addsi3} (nil)
(expr_list:REG_EQUIV (plus:SI (reg/f:SI 14 a6)
(const_int -16 [0xfffffff0]))
(nil)))
(insn 92 88 93 6 (set (mem/c:SI (reg:SI 13 a5) [0 D.1863+0 S4 A32])
(reg:SI 2 d2)) 16 {movsi_store} (nil)
(nil))
(insn 93 92 32 6 (set (mem/c:SI (plus:SI (reg:SI 13 a5)
(const_int 4 [0x4])) [0 D.1863+4 S4 A32])
(reg:SI 3 d3 [orig:2+4 ] [2])) 16 {movsi_store} (nil)
(nil))
;; End of basic block 6, registers live:
14 [a6] 15 [a7] 22 [vAP] 28
;; Start of basic block 7, registers live: 14 [a6] 15 [a7] 22 [vAP] 28
(code_label 32 93 55 7 2 "" [2 uses])
(note 55 32 98 7 [bb 7] NOTE_INSN_BASIC_BLOCK)
(insn 98 55 99 7 (set (reg:SI 13 a5)
(const_int -16 [0xfffffff0])) 17 {movsi_short_const} (nil)
(nil))
(insn 99 98 100 7 (parallel [
(set (reg:SI 13 a5)
(plus:SI (reg:SI 13 a5)
(reg/f:SI 14 a6)))
(clobber (reg:CC 21 cc))
]) 29 {addsi3} (nil)
(expr_list:REG_EQUIV (plus:SI (reg/f:SI 14 a6)
(const_int -16 [0xfffffff0]))
(nil)))
(insn 100 99 33 7 (set (reg:SI 13 a5)
(mem/c:SI (reg:SI 13 a5) [0 D.1863+0 S8 A32])) 15 {movsi_load} (nil)
(nil))
(insn 33 100 103 7 (set (reg:SI 1 d1 [ <result> ])
(reg:SI 13 a5)) 14 {movsi_regmove} (nil)
(nil))
(insn 103 33 104 7 (set (reg:SI 12 a4)
(const_int -12 [0xfffffff4])) 17 {movsi_short_const} (nil)
(nil))
(insn 104 103 105 7 (parallel [
(set (reg:SI 12 a4)
(plus:SI (reg:SI 12 a4)
(reg/f:SI 14 a6)))
(clobber (reg:CC 21 cc))
]) 29 {addsi3} (nil)
(expr_list:REG_EQUIV (plus:SI (reg/f:SI 14 a6)
(const_int -12 [0xfffffff4]))
(nil)))
(insn 105 104 34 7 (set (reg:SI 12 a4)
(mem/c:SI (reg:SI 12 a4) [0 D.1863+0 S8 A32])) 15 {movsi_load} (nil)
(nil))
(insn 34 105 38 7 (set (reg:SI 2 d2 [orig:29 <result>+4 ] [29])
(reg:SI 12 a4)) 14 {movsi_regmove} (nil)
(nil))
(note 38 34 41 7 NOTE_INSN_FUNCTION_END)
(insn 41 38 42 7 (set (reg:SI 0 d0)
(reg:SI 1 d1 [ <result> ])) 14 {movsi_regmove} (nil)
(nil))
(insn 42 41 48 7 (set (reg:SI 1 d1 [orig:0+4 ] [0])
(reg:SI 2 d2 [orig:29 <result>+4 ] [29])) 14 {movsi_regmove} (nil)
(nil))
(insn 48 42 60 7 (use (reg/i:DI 0 d0)) -1 (nil)
(nil))
;; End of basic block 7, registers live:
0 [d0] 1 [d1] 14 [a6] 15 [a7] 22 [vAP]
(note 60 48 0 NOTE_INSN_DELETED)
For my target
do, d1, d2 are the argument registers
#define FRAME_POINTER_REQUIRED 0
Can anyone shed some light as to why this might be happening?