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Re: Modifying ARM code generator for elimination of 8bit writes - need help
- From: Rask Ingemann Lambertsen <rask at sygehus dot dk>
- To: Wolfgang Mües <wolfgang at iksw-muees dot de>
- Cc: gcc at gcc dot gnu dot org
- Date: Fri, 20 Oct 2006 14:34:42 +0200
- Subject: Re: Modifying ARM code generator for elimination of 8bit writes - need help
- References: <200605282223.33002.wolfgang@iksw-muees.de> <20060806000510.GA22198@sygehus.dk> <200608121440.49614.wolfgang@iksw-muees.de> <200610021242.04233.wolfgang@iksw-muees.de>
On Mon, Oct 02, 2006 at 12:42:04PM +0200, Wolfgang Mües wrote:
> Now it's time to give a big "thank you" to all persons involved,
> ecpecially Rask Ingemann Lambertsen with his invaluable help.
>
> As I started this project, I feared that I would never succeed, and
> now ... the modified compiler is used about 3 month now, and DSLINUX
> with this crude modification is working fine with 36 MBytes RAM
> available, and has a good future now.
I'm glad to hear that it works. I have a few improvements I'd like to
make, but for the next few months, my focus will be on getting my 16-bit x86
into GCC 4.3.
You can take a look at the relout_outqi pattern. It uses two scratch
registers: One for the address and one as a scratch register for swpb. It is
worth investigating if you can safely trash the input operand, since the
reason we have an output reload is because a pseudo register got a stack
slot instead of a hard register. I.e. reload shouldn't expect the value in
operand 1 to be preserved for use in a later insn. But I think a reload
expert should comment on this.
--
Rask Ingemann Lambertsen