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Re: paired register loads and stores
- From: David Edelsohn <dje at watson dot ibm dot com>
- To: "Erich Plondke" <eplondke at gmail dot com>
- Cc: gcc <gcc at gcc dot gnu dot org>
- Date: Fri, 29 Sep 2006 09:08:51 -0400
- Subject: Re: paired register loads and stores
- References: <deb8826f0609282227x6b7e96f7s141fc04abaf78372@mail.gmail.com>
>>>>> Erich Plondke writes:
Erich> rs6000 and Sparc ports seem to use a peephole2 to get the ldd or lfq
Erich> instructions (respectively), but it looks like there's no reason for
Erich> the register allocater to allocate registers together. The peephole2
Erich> just picks up loads to adjacent memory locations if the allocater
Erich> happens to choose adjacent registers (is that correct?) or the
Erich> variables are specified as living in hard registers with the help
Erich> of an asm.
On both rs6000 and sparc, the code includes a test that the
registers are adjacent. See registers_ok_for_quad_peep() in rs6000.md and
rs6000.c, and equivalent in sparc.
David