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Re: Modifying ARM code generator for elimination of 8bit writes - need help
On Thu, Jul 20, 2006 at 03:27:49PM +0200, Rask Ingemann Lambertsen wrote:
> (define_expand "reload_outqi"
> [(clobber (match_operand:QI 0 "memory_operand" "=Q"))
> (clobber (match_operand:DI 2 "register_operand" "=&r"))
> (set (match_dup 4) (match_dup 5))
> (parallel [
> (set (match_dup 6)
> (match_operand:QI 1 "register_operand" "r"))
> (clobber (match_dup 3))]
> )]
[...]
I should perhaps explain how this works. Let's say operand 0 is (mem:QI
(reg:SI 0)), operand 1 is (reg:QI 1) and operand 2 is (reg:DI 2). We then
get:
(clobber (mem:QI (reg:SI 0)))
(clobber (reg:DI 2))
(set (reg:SI 3) (reg:SI 3)) ; {*arm_movsi_insn}, optimized away later.
(parallel [
(set (mem:QI (reg:SI 0)) (reg:QI 1))
(clobber (reg:QI 2))
]) ; {_arm_movqi_insn_swp}
If operand 0 is (mem:QI (plus:SI (reg:SI 0) (const_int 16))), we get:
(clobber (mem:QI (reg:SI 0)))
(clobber (reg:DI 2))
(set (reg:SI 3)
(plus:SI (reg:SI 0) (const_int 16))) ; {*arm_addsi3}
(parallel [
(set (mem:QI (reg:SI 3)) (reg:QI 1))
(clobber (reg:QI 2))
]) ; {_arm_movqi_insn_swp}
I'll rewrite it to make clearer what is going on. Also, the two clobber
expressions have no purpose in the insn stream. They only exist because all
external operands must be declared using match_operand somewhere in the RTL
template and RTL offers no good way of doing that in a case like this one.
--
Rask Ingemann Lambertsen