Re: Modifying ARM code generator for elimination of 8bit writes - need help

[Rask Ingemann Lambertsen <rask at sygehus dot dk>]

On Fri, Jun 02, 2006 at 08:23:49AM +0200, Wolfgang Mües wrote:
> Rask,
> 
> (_only_ adding the clobber statement),
> I get

> >0/newlib/li bc/argz/argz_create_sep.c:60: error: unrecognizable insn:
> (insn 192 21 24 0 (set (reg:QI 1 r1) (reg:QI 4 r4)) -1
>      (nil) (nil))
> 
> What do you mean with
> 
> > You will also have to modify any code which 
> > expands this pattern accordingly.

The rest of the ARM backend presently assumes that the pattern has the form

(set (operand:QI 0) (operand:QI 1))

but now we've changed it to

(parallel [(set (operand:QI 0) (operand:QI 1))
	   (clobber (operand:QI 2))
])

so that's why you get "unrecognizable insn" errors now. Any place which
intended to generate an *arm_movqi_insn has to add a clobber also. For a
start, this means the "movqi" pattern.

There may be a faster way of seeing if the modification is going to work for
the DS at all. I noticed from the output template "swp%?b\\t%1, %1, [%M0]"
that "swp" takes three operands. I don't know ARM assembler, but you may be
able to choose to always clobber a specific register. Make it a fixed register
(see FIXED_REGISTERS), refer to this register directly in the output template
and don't add a clobber to the movqi patterns. IMHO, that's an acceptable hack
at an experimental stage. If the resulting code runs correctly on the DS, you
can then undo the FIXED_REGISTERS change and add the clobber statements.

-- 
Rask Ingemann Lambertsen