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Re: Modifying ARM code generator for elimination of 8bit writes - need help
> > There are a couple of complications that spring to mind. The different
> > addressing modes and the fact that swp clobbers a register are the most
> > immediate ones.
> >
> > You'll need to modify at least the movqi insn patterns, memory
> > constraints and the legitimate address stuff. I'm not sure about the
> > clobber, that might need additional reload-related machinery.
>
> I suspect it would be better to make GCC do halfword stores instead
> (read/modify/write).
Does gcc have mechanisms for doing this, or would you have to hide it all
inside the movqi pattern?
If the latter I don't see much difference in terms of implementation. strb and
strh use different addressing modes :-)
Whether ldrh/strh are faster than swpb probably depends whether your cpu
supports unaligned loads. It also means byte stores are no longer atomic,
though I don't know whether that is important.
Paul